RISC-V has gained attention in recent times for its open-source ISA, modularization, and extensible features that facilitate customization in various edge computing applications. These RISC-V-based modern processors often use a pipeline architecture and frequently load data from memory to enhance the throughput. However, bubbles due to load-word (Data hazard) hazards will inevitably arise in the pipeline, causing degradation in CPI. The out-of-order pipeline processor can handle the bubble through scheduling but it introduces WAR (write after read) and WAW (write after write) making architecture more complex and not suitable for low-power applications. Hence, this paper proposes a novel lw-driven bubble-free five-stage pipelined RV32I processor core based on open-source RISC-V ISA, i.e. the proposed core is an in-order RISC-V processor core that can handle bubbles without any clock penalty due to stall. The core is implemented using Verilog HDL and prototyped on the commercially available Xilinx Artix-7 FPGA with a resource requirement of 1271 LUTs and 641 Registers. A notable 19.37% improvement in CPI is achieved compared to the state-of-the-art stalling algorithm on the same RV32I processor core. Comparing the proposed design to the traditional stall method, the score improved significantly by 14%, achieving a core mark score of$1.06~CoreMark/MHz$. The dynamic power consumption of the core is$0.9~mW/MHz$and is best suited for energy-constrained applications.

In the modern era, FPGA-based soft-core processors have gained much attention in space applications due to their flexibility and ease of integration. In such applications, radiation can produce a Single Event Upset (SEU) in CMOS devices that may lead to severe errors in microprocessors. The instruction decoder is one of the most critical components of a microprocessor. Any error in the instruction decoder due to SEU may destroy the flow of the program, and it may lead to complete system failure. Hence, a novel parity-based fault-tolerant instruction decoder architecture is proposed for dual-core processors implemented on FPGAs. In case of occurrence of SEU, the instruction decoders of two cores are swapped for fault-masking against single-bit error. Looking at the increased adaptability of RISC-V ISA, the proposed fault-tolerant instruction decoder is integrated with an in-house designed RV32IM processor using Verilog HDL. Further, the proposed fault-tolerant processor architecture is prototyped on commercially available NEXYS4 DDR FPGA board by employing the soft error mitigation (SEM) IP core of Xilinx Inc. to inject SEU in real time to study the fault tolerance capability. The proposed design is compared with the state-of-the-art SEU mitigation approaches. The main advantage of the proposed architecture is that the LUT (Look up table) overhead is 167.06% less, and power overhead is 46.87% less compared to the conventional triple modular redundancy (TMR) approach to mitigate SEU. The proposed design is able to provide 71.2% fault tolerance compared to the unprotected design.

Electrocardiogram (ECG) beat behaves as a non‐linear and non‐stationary signal. Since most of the existing data processing tools are poor alternatives for processing such signals, Hilbert–Huang transform (HHT) proves to be an efficient method as it deals with a time‐varying frequency spectrum. In this study, a new and efficient methodology is proposed using HHT for feature selection which includes a set of essential features such as weighted mean frequency, Kolmogorov complexity and other statistical features (median, standard deviation, kurtosis, skewness and central moment) computed from the intrinsic mode functions extracted using the empirical mode decomposition (EMD) algorithm. Further, one‐against‐one multi‐class support vector machine is employed for the classification of six generic ECG beats, namely: normal, left bundle branch block, right bundle branch block, premature ventricular contraction, paced beat and atrial premature beat. The classification process in this study yields better results than existing methodologies in terms of classification accuracy equal to 99.51% along with sensitivity, specificity and positive predictivity of 98.64, 99.77 and 98.17%, respectively.

Abstract In the last few decades, patients demand the data integrity and confidentiality of their Electrocardiography (ECG) signal for remote diagnosis through the network. In this context, a Dynamic Hash key‐based stream cipher for a cryptosystem is proposed to transmit the ECG signal to maintain integrity and confidentiality. The novelty of this proposed methodology is based on real‐time dynamic non‐recursive pseudorandom keystream using dynamic Toeplitz hash value‐based RC4 algorithm, unlike the existing static key‐based stream ciphers. The Toeplitz hash value (HV) is constructed from the sequence generated using non‐singular sequence folding‐based nonlinear feedback function expressed in algebraic normal form. The proposed design is realized using Verilog hardware description language (HDL) to construct the non‐recursive dynamic key stream sequence and prototyped on existing hardware Field‐programmable gate array (FPGA) device Virtex 5 xc5vlx110t‐2ff1136. The generated dynamic binary key stream sequence is analysed for key size, correlation and further verified by randomness tests using National Institute of Standards and Technology statistical test suites. The laboratory experiment is carried out with the existing two FPGA boards to prototype the proposed hardware cryptosystem for the encryption and decryption of real time ECG signal. The implementation result in the FPGA device accomplishes with the initial latency of 257 clock cycles and improved data throughput of 534Mbps than the existing design. Copyright © 2016 John Wiley & Sons, Ltd.

Abstract In this paper, a new algorithm to construct the non‐linear‐based Boolean function using non‐singular sequence folding technique is proposed to generate pseudorandom binary key sequence for cryptographic processor. Unlike the conventional methodology to generate recursive pseudorandom nibble of 15 (60‐bit) from minimum seed of four bits, the proposed algorithm has the novelty to generate non‐recursive pseudorandom nibble of 63 (252‐bit) from the same minimum seed of four bits. In this proposed algorithm, a given binary sequence is converted to de Bruijn sequence and folded to minimum state with the strategy of binary encoding, which supports to determine the non‐linear Boolean function. Further, the next state functions with minimum logic complexity is formulated using the algebraic normal form to generate non‐recursive pseudorandom binary sequence. The key stream analysis is performed, and randomness tests for the generated pseudorandom binary sequence (key stream) is validated using National Institute of Standards and Technology test suite. The proposed algorithm in this paper has improved in terms of sequence size and number of stages compared with existing algorithms. Copyright © 2015 John Wiley & Sons, Ltd.

CORDIC (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of CORDIC algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations to${\mbi{n}}/{\bf 2}$plus additional iterations including rotation and scale factor calculation and compensation for${\mbi{n}}$bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to$({\bf 3}{\mbi{n}}/{\bf 8}) + {\bf 1}$for${\mbi{n}}$bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency CORDIC algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid CORDIC algorithm along with first order hardware architecture.

Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2n(n=6, 7…13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.