Look-up Table (LUT) mapping and optimization is an important step in Field Programmable Gate Arrays (FPGAs) design. The effectiveness of LUT synthesis improved dramatically in the last decades, thanks to optimization and mapping innovations naturally tailored for FPGAs. In this paper, we develop a new LUT-based optimization flow that is tailored for the synthesis of Application-Specific Integrated Circuits (ASICs) rather than FPGAs. We enhance LUT mapping to consider the literal/AIG cost of LUT nodes. We extend traditional Boolean methods to simplify and re-shape LUT-networks, targeting the best AIG/mapped-network implementation, after decomposition. Intuitively, literal-driven LUT packing behaves as a powerful fanin-bound node elimination, unveiling higher-order Boolean simplification opportunities. We embed our proposed LUT-based optimization flow, area oriented, in a commercial synthesis tool. Using our methodology, we improve 12 of the best area results in the EPFL synthesis competition. Employed in a commercial EDA flow for ASICs, our LUT optimization reduces area by 1.80%, total negative slack by 0.39%, and switching power by 1.72%, after physical implementation, at 5% runtime cost.

SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesis applications within EDA. In this paper, we focus on the development of a highly efficient, synthesis-oriented, SAT-sweeping engine. We introduce a new algorithm to guide initial simulation, which strongly reduces the number of false candidates for merge, thus increasing the computational efficiency of the sweeper. We revisit the SAT-sweeping flow in light of practical considerations for synthesis, with the aim of proving all valid merges and ensuring fast execution. Experimental results confirm remarkable speedup deriving from our methodology, up to 10× for large combinational networks, and better QoR as compared to previous SAT-sweeping implementation. Embedded in a commercial synthesis flow, our proposes SAT-sweeper enables area and power savings of 1.98% and 1.81%, respectively, with neutral timing at negligible runtime overhead, over 36 testcases.

In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%.

This brief proposes the use of four-level forms in the memristive material implication (M-IMP) logic. M-IMP is a promising approach to perform stateful logic in memristive nonvolatile memories. In such a design technique, a given Boolean function is evaluated as a sequence of instructions, making logic synthesis methods necessary to attain the shortest sequence. In comparison to previous work, experimental results have shown an average reduction of 40% when evaluating the tradeoff between the numbers of instructions and memristive devices.

Side-channel attacks are currently one of the most powerful attacks against implementations of cryptographic algorithms. They exploit the correlation between the physical measurements (power consumption, electromagnetic emissions, timing) taken at different points during the computation and the secret key. Some of the existing countermeasures offer a protection against one specific type of side channel only. We show that it can be a bad practice which can make exploitation of other side-channels easier. First, we perform a power analysis attack on an FPGA implementation of the Advanced Encryption Standard (AES) which is not protected against side-channel attacks and estimate the number of power traces required to extract its secret key. Then, we repeat the attack on AES implementations which are protected against fault injections by hardware redundancy and show that they can be broken with three times less power traces than the unprotected AES. We also demonstrate that the problem cannot be solved by complementing the duplicated module, as previously proposed. Our results show that there is a need for increasing knowledge about side-channel attacks and designing stronger countermeasures.

Transistor scaling is the major contributor toward continuous improvement of circuit performance. However, the reduction of transistor dimensions increases several fabrication and design challenges. In this sense, several post CMOS devices are being investigated. Recently, the magnetoresistive spin-diode was proposed and the possibility to implement logic gates exploiting this kind of device has been demonstrated. The spin-diode technology has the INV, NOR2 and XNOR2 as basis logic functions, which is quite different from the CMOS basic gates. This paper proposes an algorithm that improves the state-of-the-art synthesis algorithm for the spin-diode technology. Also, this paper presents some optimized designs of functions that appear frequently in circuits. Results show a reduction of more than 3% in number of diodes, compared to the state-of-the-art algorithm.

This paper presents a new approach for Boolean decomposition based on the Boolean difference and cofactor analysis. Two simple tests provide sufficient and necessary conditions to identify AND and exclusive-OR (XOR) decompositions. The proposed method can decompose an n-input function in O(n • log n) cofactor and O(n) equivalence test operations. Recently, 2-to-1 multiplexers (MUX) have also been used to perform such decomposition. However, MUX with more inputs has been neglected. We provide sufficient and necessary conditions to obtain MUX decompositions of functions with an arbitrary number of inputs.

This work presents an efficient algorithm to obtain a material implication (IMPLY) expression from a sum-of-products (SOP). The resulting expression is computable with two work memristors. The proposed method has linear time complexity with respect to the SOP size. Comparison to previous work shows a reduction on the average number of IMPLY operations when applying the proposed method.

This paper presents two contributions to logic synthesis for memristive stateful logic. Firstly, we demonstrate the necessity to correct results provided by existing logic synthesis methods to ensure the expected computation. Secondly, we propose the concept of multi-memristor implication as a generalization of multi-input implication. Experimental results have shown a reduction of 6.5% in the number of operations when compared to previous works.

This paper presents a novel analytical delay model to perform fast estimation of signal delay propagation over buffer chain under time-dependent dielectric breakdown (TDDB) aging effect. The proposed model considers all gate-to-drain, gate-to-source and gate-to-bulk breakdowns effects, and relies on accurate modeling of TDDB. In comparison to SPICE simulation, based on BSIM4 transistor model, experimental results have shown an average error of 1.65%, whereas 98% of the cases present an estimation error of at most 5%.

This paper presents an accurate analytical delay model for CMOS inverter considering both subthreshold and superthreshold operating regions. Previous related work are either only valid for a specific operating condition or assume a step input. Therefore, that is the first approach to consider both different operating regions and input transition time. Moreover, the proposed model also considers several second order effects that influence the CMOS inverter dynamic behavior. Compared to electrical simulations based on BSIM4 transistor model the proposed delay model presents an average error of 2.3% and the worst case error of 6.6%.

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.