Capability architectures for memory safety have traditionally required expanding pointers and radically changing microarchitectural structures throughout processors, while only providing superficial hardening. We hence propose Cryptographic Capability Computing (C3) - the first memory safety mechanism that is stateless to avoid requiring extra metadata storage. C3 retains 64-bit pointer sizes providing legacy binary compatibility while imposing minimal touchpoints. Pointers are encrypted to unforgeably (within cryptographic bounds) reference each object. Data is encrypted even in caches and entangled with pointers for both spatial and temporal object-granular protection. Pointers become like unique keys for each allocation. C3 deploys a novel form of prediction for address translation that mitigates performance overheads even when addresses are partially encrypted. Use of a low-latency, low-area cipher from the NIST Lightweight Cryptography project avoids delaying loads by readying a data keystream by the time data is returned from the L1 cache. C3 is compatible with legacy binaries. Simulated performance overhead on SPEC CPU2006 is negligible with no memory overhead, which is a big leap forward compared to the overheads imposed by past memory safety approaches. C3 effectively replaces inefficient metadata with efficient cryptography.

We present the design of a novel low latency, bit length parameterizable cipher, called the "K-Cipher". K-Cipher is particularly useful to applications that need to support ultra low latency encryption at arbitrary ciphertext lengths. We can think of a range of networking, gaming and computing applications that may require encrypting data at unusual block lengths for many different reasons, such as to make space for other unencrypted state values. Furthermore, in modern applications, encryption is typically required to complete inside stringent time frames in order not to affect performance. K-Cipher has been designed to meet these requirements. In the paper we present the K-Cipher design and discuss its rationale. We also present results from our ongoing security analysis which suggest that only 2 to 4 rounds are sufficient to make the cipher operate securely. Finally, we present synthesis results from 2-round 32-bit and 64-bit K-Cipher encrypt datapaths, produced using Intel’s ® 10 nm process technology. Our results show that the encrypt datapaths can complete in no more than 767 psec, or 3 clocks in 3.9-4.9 GHz frequencies, and are associated with a maximum area requirement of 1875 m2.

We present a cryptographic construction called IVP and study its security properties. IVP is a three level confusion-diffusion network that supports confidentiality and data integrity without requiring any message expansion of the content, such as, for example, for the computation of a MAC. We demonstrate that IVP is in the recently proposed class of cryptographic constructions called `Random Oracles according to Observer functions' (RO2). These constructions support a new notion of data integrity called `implicit' data integrity, which is based on the fact that user data usually demonstrate some patterns. If some ciphertext becomes corrupted, then the resulting plaintext no longer demonstrates such patterns. Thus, defense against data corruption attacks becomes possible by hardening the computation of ciphertext values, the plaintext of which demonstrates patterns. The encryption key is considered unknown.We show that IVP supports implicit data integrity and is secure in input perturbing and oracle replacing adversary models. The security of IVP is associated with a pattern which is frequently encountered among client and server data. This is the pattern of encountering 4 or more 16-bit words being equal to each other in a set of 32 words. The cryptographic strength of IVP is 30.215 bits, which is sufficient for defending against on-line data corruption and content replay attacks. Computationally, IVP is much lighter than other authenticated encryption approaches requiring only two additional rounds of AES, beyond the AES standard encryption rounds in the critical path. These correspond to some minimal computation overhead.

We address a well known problem of computer science, the problem of computing the probability that a given number of people m > 1 have the same birthday from among the members of a larger set of cardinality n ≥ m. The solution to this problem for m = 2 is well known and is usually referred to as the ‘birthday surprise probability’. A solution for m = 3 is also known and appears in the 2004 paper by DasGupta [The matching, birthday and the strong birthday problem: a contemporary review, Journal of Statistical Planning and Inference]. Further approximations to the solution of the related problem of computing the minimum number of people to interview until m people with the same birthday are found are presented in the seminal work by Klamkin and Newman [Extensions on the birthday surprise, Journal of Combinatorial Theory, 1967]. In this paper we present a new non-recursive approximation for the birthday probability applicable to any value of m > 1, which yields results that are experimentally proven accurate under the assumption that the number of birthdays is significantly larger than the number of people. Our expression is easy to compute, non-recursive, and applicable to values of m that can be arbitrarily larger than 2 or 3. We verify the validity of our result computing the birthday probability for different values of m, over billions of sets of random values generated using the Intel ® RDRAND hardware random number generation instruction. Our solution is based on a novel tree-based description of the event space which, if used, allows for the computation of the birthday probability efficiently and without involving recursions or multinomial distributions.

Three-dimensional (3D) integration using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. This paper examines the hype, myths, and realities of 3D IC testing. We describe a number of testing and DfT challenges, and present some solutions being advocated for the challenges of “What to Test”, “How to Test”, and “When to Test”. Techniques highlighted in this paper include: (i) testing of the silicon interposer; (ii) pre-bond TSV testing; (iii) cost modeling and test-flow selection; (iv) a reconfigurable built-in self-test infrastructure.

Modern CMOS technology enables the integration of billions of transistors on a single chip. Emerging three-dimensional (3D) stacking techniques using through-silicon vias (TSVs) promise even higher integration by combining multiple dies in a single package. In order to keep the test cost low and enhance field reliability, there is a need to re-think conventional test practices, such as test-data compression and online testing, as well as test-application techniques and fault diagnosis. Traditional hardware-based on-chip decompression solutions are limited to compression techniques that do not require large hardware overhead for decompression. However, today's system-on-chip designs (SoCs) offer resources, such as embedded processors and large amounts of fast embedded memories, that can be exploited for efficient on-chip test application, online testing, and diagnosis using software-based compression. Examples of such systems are 3D ICs with wide-I/O DRAM or traditional ICs with embedded DRAM (eDRAM). We propose a test and diagnosis solution that makes use of software-based decompression of deterministic scan-test pattern and allows for test application from on-chip DRAM to the logic die, extending traditional hardware-based methods and allowing for online scan-based test and diagnosis. This solution therefore targets SoCs that contain, in addition to a microprocessor, multiple digital-logic cores and glue logic, all of which need to be tested using scan test patterns. Simulation results for benchmarks show that we can achieve high test-data compression, comparable with what is obtained using commercial tools, as well as high-resolution on-chip diagnosis with negligible hardware and test-time overhead.

Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be screened early in the manufacturing flow. We propose a non-invasive method for pre-bond TSV test and diagnosis that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their RC parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect resistive open and leakage faults. In addition, we use duty-cycle detectors to measure the duty cycle of the oscillation signal. These measurements provide additional information for fault analysis and hence increase the diagnosis accuracy. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. We also present a method to create a regression model based on artificial neural networks to predict the fault size. As input, this model uses both the oscillation period and the duty cycle measured at multiple different voltage levels. The model classifies the type of the fault and predicts its size. Moreover, the regression model can effectively determine whether a TSV has both leakage and resistive-open defects. Results on fault-diagnosis effectiveness are presented through HSPICE simulations using realistic models for a 45nm CMOS technology. The estimated DfT area cost of our method is negligible for dies of realistic size.

Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). This work provides solutions to new challenges related to 3D test content, test access, diagnosis and debug. We analyze the the impact of thermo-mechanical stress due to TSV fabrication process on test quality. We propose a test-generation flow that takes TSV-induced stress into account by using stress-aware circuit models. Pre-bond TSV test is a challenge due to limited accessibility of TSV at the pre-bond stage. We develop a non-invasive method for TSV test and diagnosis using ring oscillators, duty-cycle detectors, and a regression model based on artificial neural networks. In order to efficiently deliver test content, 3D design-for-test (DfT) architectures are needed. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time. Finally, post-silicon debug is a major challenge due to continuously increasing design complexity. We develop a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies that significantly increases the observation window compared to traditional methods that use trace buffers.

3-D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3-D ICs. Recent work on the optimization of 3-D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter space. In realistic scenarios, the assumed values for parameters such as test power and pattern count of logic cores, which are used for optimizing the test architecture for a die, may differ from the actual values that are known only after the design stage. In a 3-D setting, a die can be used in multiple stacks with different properties. As a result, the originally designed test architecture is no longer optimal, which leads to an undesirable increase in the test cost. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations. We formulate a mathematical model for the robust test-architecture optimization problem, and propose an efficient heuristic to solve the problem even for large designs in reasonable time. The proposed optimization framework is evaluated using the ITC'02 SoC benchmarks and we show that robust solutions are superior to single-point solutions in terms of average test time when there are uncertainties in the values of input parameters.

Silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. We propose a low-cost debug architecture for massive signal tracing in ICs that integrate fast DRAM, such as 2D-ICs with embedded DRAM or 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. During a debug session, the entire observation window is divided into intervals and a signature is calculated for each observed interval using a multiple-input signature register. At run time, intervals containing erroneous bits are identified by comparing their signature with pre-calculated “golden” signatures that are stored in the DRAM a priori. Only failing intervals including their time stamp are stored into DRAM, which allows for a more efficient use of the memory, resulting in a larger observation window. The proposed method does not require multiple iterations or intermediate processing steps, hence it can be used during functional testing with minimum time overhead associated with the upload of golden signatures and the download of stored debug data to external equipment. We have created a Verilog RTL model for the proposed architecture, synthesized it using a 45 nm CMOS library, and verified its functionality by simulation. The results show that the observation window can be increased by orders of magnitude compared to prior work at comparable hardware cost.

IMEC and Cadence have jointly developed a 3D-DfT architecture that serves both 2.5D- and 3D-SICs. Originally targeting stacks of monolithic logic-only dies, over time this architecture has been extended to include (1) memory-on-logic stacks, (2) complex SOCs, and (3) multi-tower stacks. We have defined and implemented a full automation flow based on Cadence' RTL Compiler and Encounter Test. To demonstrate the capabilities of the 3D-DfT architecture and associated EDA flow, we designed a 3D-DfT Demonstrator circuit as part of an IMEC 3D chip stack nicknamed `Vesuvius-3D'. This test vehicle consists of two identical dies of 8.1×8.1mm2in 65nm CMOS processed by GLOBALFOUNDRIES and IMEC. In this paper, we report on the design, test generation, processing, and pre-bond and post-bond measurement results of this 3D-DfT Demonstrator.

Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and reliability of 3-D stacked integrated circuits, hence these defects need to be screened early in the manufacturing flow. Before wafer thinning, TSVs are buried in silicon and cannot be mechanically contacted, which severely limits the test access. Although TSVs become exposed after wafer thinning, probing on them is difficult because of TSV dimensions and the risk of probe-induced damage. To circumvent these problems, we propose a non-invasive method for pre-bond TSV test that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their resistor-capacitor parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect the resistive open and leakage faults. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. We provide a method to create a regression model to predict the defect size for a given measured period period of the ring oscillator, and a method for accuracy analysis. Results on fault detection effectiveness are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The estimated design for testability area cost of our method is negligible for realistic dies.

Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be screened early in the manufacturing flow. Before wafer thinning, TSVs are buried in silicon and cannot be mechanically contacted, which severely limits test access. Although TSVs become exposed after wafer thinning, probing on them is difficult because of TSV dimensions and the risk of probe-induced damage. To circumvent these problems, we propose a non-invasive method for pre-bond TSV test that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their RC parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect resistive open and leakage faults. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. Results on fault detection effectiveness are presented through HSPICE simulations using realistic models for 45nm CMOS technology. The estimated DfT area cost of our method is negligible for realistic dies.

Today's technology allows for the integration of many cores in a single die, for instance, in core-based SoCs, and an even larger number of cores are likely to be integrated over multiple layers in a 3D stack. In order to minimize test cost, the test architecture in a core-based SOC is optimized for minimum test time. Optimization methods in use today assume that all relevant input parameters, such as core test time and power consumption during test, are known at the design stage. However, these parameters can change after manufacturing and, in that scenario, the originally designed test architecture may no longer be optimal. Moreover, conventional optimization methods have to consider worst-case estimates for all input parameters to ensure feasibility, which can result in conservative and hence expensive solutions. We propose the use of robust optimization for test-architecture design and test scheduling. This goal of this approach is to find a solution that remains close to optimal in the presence of parameter variations. Experimental results for the ITC'02 SoC benchmarks show that, compared to optimization methods that target only a single point in the input-parameter space, robust optimization can better optimize test time in the presence of parameter variations.

3D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3D-SICs. Recent work on the optimization of 3D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter space. In realistic scenarios, the assumed values for parameters such as test power and pattern count of logic cores, which are used for optimizing the test architecture for a die, may differ from the actual values that are known only after the design stage. In a 3D setting, a die can be used in multiple stacks each with different properties. As a result, the originally designed test architecture might no longer be optimal, which leads to an undesirable increase in the test cost. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations. We use integer linear programming (ILP) to formulate the robust test-architecture optimization problem, and the resulting ILP model serves as the basis for a heuristic solution that scales well for large designs. The proposed optimization framework is evaluated using the ITC'02 SoC benchmarks and we show that robust solutions are superior to single-point solutions in terms of average test time when there are uncertainties in the values of input parameters.

Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault testing. We show quantitatively using the SDQL metric that test quality is significantly reduced if the test patterns are generated with TSV stress-oblivious circuit models. We evaluate the impact on TSV stress on delay testing by considering layouts for several 3D logic-on-logic benchmarks. The test escape rate is higher for processes with lower yields. Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count. We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation.

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

Using Through-Silicon Vias (TSVs) in three-dimensional stacked ICs (3D-SICs) has benefits in terms of interconnect density, performance, and power dissipation. For 3D-SICs, an extension of the Design-for-Test architecture based on die-level wrappers is required to enable pre-bond die testing as well as modular post-bond die and interconnect testing. This paper presents an approach that automates the insertion of die wrappers. Experimental results show that the user can perform automated 3D-DfT insertion through existing EDA tools with negligible area costs, and verify the proposed DfT by test pattern generation and simulation.