Recent expansion of cloud services is accelerating the development of flexible and fast network technologies. Software and hardware co-design of data plane packet processing pipelines is attracting growing attentions to achieve both flexibility and high-speed performance at the same time. In this paper, we propose a technique called flow cache cleansing for the data plane of a software switch co-designed with an FPGA hashing pipeline. If a lot of small flow rushes to the target system, the flow cache of the software switch is contaminated, causing performance degradation and instability. Our contribution is to clarify the factor determining the performance and overcome the stability issue. Experimental results show that the proposed method can mitigate the flow cache pollution and achieve throughput as much as several times faster than some commodity technologies. Moreover, the results demonstrate that the proposed method produced at least several times higher performance stability than existing technologies.

Field-programmable gate arrays (FPGAs) are extremely advanced with regard to high performance; they are becoming one of the primary device choices to realize high-performance computing (HPC). In this work, we propose an FPGA-based accelerator for the two-dimensional (2D) finite difference method (FDM) with the implicit scheme and implement a 2D unsteady-state heat conduction simulation using red/black successive over-relaxation (SOR). The accelerator consists of a 2D single-instruction multiple-data (SIMD) array processor, which has pipelined processing elements (PEs) including 32-bit floating point calculation units. This processor can avoid the memory-access bottleneck and perform with high operating efficiency and low waiting time for data transfer by applying the proposed control method with synchronous shift data transfer. We demonstrate that the experimental hardware implemented on an Altera Stratix V FPGA (5SGSMD5K2F40C2N) reaches a 99.83% operating rate of the calculation units for the computation of red/black SOR. In addition, it is approximately six times faster than GPU computing on an NVIDIA GeForce GTX 770 for a 32-bit floating-point calculation of a printed circuit board (PCB) heat conduction simulation, and it is about eight times faster than an NVIDIA Tesla C2075 for the same calculation.

This paper presents a software-hardware co-operative protocol processor for a 10 gigabit Ethernet passive optical network (10G-EPON), designed with a software-hardware division technique that focuses on the throughput and timing-accuracy requirements. This protocol processor consists of frame-processing hardware to meet the timing requirements, an interface to absorb the speed difference between software and hardware, and software to implement additional protocols. This protocol processor enables network operators to install additional service protocols adaptively for their own services. The 10G-EPON system with this protocol processor properly worked in the experiment.

To reduce the power consumption of optical network units (ONUs), we propose a dual buffer architecture and control schemes for short-time shaping and frame loss prevention. The dual-buffer architecture uses a small-capacity buffer to shut down a large capacity buffer, which is always active in a conventional architecture. The short-time shaping scheme minimizes the architecture overhead by cooperative operation with the optical line terminal (OLT). The frame-loss-prevention scheme is a fail-safe scheme for the cooperative operation. Simulations and experiments show that our proposed approach reduces ONU power consumption without frame loss even while the ONU continuously receives traffic such as video.