Demo Data from EDBT 2026 / reviewers in the wild / expert
Tetsuya Fujimoto
dblp:47/1153
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › functional verification › system-level verification
hardware/software co-verification |
0.0 | 1 | 1996 | VLSI Design and System Level Verification for the Mini-Disc · DAC 1996 |
Electronic design automation › hardware verification and test › functional verification
system-level verification |
0.0 | 1 | 1996 | VLSI Design and System Level Verification for the Mini-Disc · DAC 1996 |
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design |
0.0 | 1 | 1996 | VLSI Design and System Level Verification for the Mini-Disc · DAC 1996 |
Methods — techniques the papers use, named apart from their topics
emulation · 0.0concurrent design · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | A Scheduling Method for Synchronous Communication in the Bach Hardware CompilerabstractIn this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler. Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada 0001, Tetsuya Fujimoto, Takashi Kambe |
ASP-DAC | 5 |
| 1996 | VLSI Design and System Level Verification for the Mini-DiscabstractIn this paper, a new method for the design of complex multimedia ASIC is introduced.Using this design method, VLSI with embedded software and high-speed emulators can be developed concurrently.The method has proven to be eective through actual design of VLSI for audio compression and decompression in a Mini-Disc system. Tetsuya Fujimoto, Takashi Kambe |
DAC | 1 |