This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.

This paper presents a highly effective method for parallel hard fault simulation and test specification development. The proposed method formulates the fault simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs. This approach extended by parametric fault testing has been implemented as an automated tools set for IC testing.

Process variation has forever been the major fail cause of analog circuits where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach, extended by hard fault testing, has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.

The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly to the complexity of analog behavior and the lack of a fault mode. We present a new functional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance between the responses of the faulty and fault-free circuit and their distributions. The model allows fault abstraction of physical defects through structural fault modeling and perturbation estimation. The fault simulation technique uses a linear estimation of the faulty and fault-free output circuits. Techniques for fault observation and propagation are presented in order to build a hierarchical analog fault simulator.

Integrating design and test presents a good challenge in today's analog circuit manufacturing process. Designs should be made according to the sensitivity of the output to all the components. Furthermore, sensitivity can be used to observe component deviation (soft faults) and hard faults from the output. This paper presents an automated sensitivity analysis tool, called LIMSoft, which offers the possibility of sensitivity computation and analysis in order to design fault-resistant circuits and generate test vectors for both soft and hard faults. Some applications for integrating test and design are also presented.

In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value /spl plusmn//spl epsiv/. A sine wave generator and two different BISTs are proposed: the defection and translation (DandT) T-BIST approach and the frequency-counter BIST approach. Some experimental results are also presented.