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Tahsin Askar

dblp:47/1410 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 51% Electronic design automation · 26% Performance modeling and evaluation · 15%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997
Electronic design automation › physical design
routing
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997
Interconnection networks and networks-on-chip › routing algorithms
self-routing
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997
Memory systems › shared memory
distributed shared memory
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997
Performance modeling and evaluation › simulation › architectural simulation
execution-driven simulation
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997
Performance modeling and evaluation
simulation
0.011997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor · IEEE Trans. Parallel Distributed Syst. 1997

Methods — techniques the papers use, named apart from their topics

queueing analysis · 0.0performance analysis · 0.0
YearPublicationVenuePosition
1997 Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor
abstract
A multistage bus network (MEN) is proposed to overcome some of the shortcomings of the conventional multistage interconnection networks (MINs), single bus, and hierarchical bus interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the MINs and has the same bandwidth at each stage. A switch in an MBN is similar to that in a MIN switch except that there is a single bus connection instead of a crossbar. MBNs support bidirectional routing and there exists a number of paths between any source and destination pair. The authors develop self routing techniques for the various paths, present an algorithm to route a request along the path with minimum distance, and analyze the probabilities of a packet taking different routes. Further, they derive a performance analysis of a synchronous packet-switched MBN in a distributed shared memory environment and compare the results with those of an equivalent bidirectional MIN (BMIN). Finally, they present the execution time of various applications on the MBN and the BMIN through an execution-driven simulation. They show that the MBN provides similar performance to a BMIN while offering simplicity in hardware and more fault-tolerance than a conventional MIN.
Laxmi N. Bhuyan, Ravi R. Iyer 0001, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
IEEE Trans. Parallel Distributed Syst.3
1994 Performance and Reliability of the Multistage Bus Network
abstract
A Multistage Bus Network(MBN) has been proposed as a viable alternative to the existing interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the conventional Multistage Interconnection Networks(MINs) and has the same bandwidth at each stage. Due to the bidirectional nature of the MBN, there exist a number of separate paths between any source and destination pair. Some paths make a U-turn at an intermediate stage switch which is a common ancestor of the source and destination. We present self routing techniques for the various paths. We also present a performance analysis of a synchronous packet switched MBN and compare the results with those of a MIN. Finally we present a reliability analysis of the MBN and show its superiority over the MIN.
Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar
ICPP (1)3