Parallel real-time embedded applications can be modelled as directed acyclic graphs (DAGs) whose nodes represent subtasks and whose edges represent precedence constraints among subtasks. Scheduling such parallel tasks on a multicore platform with efficient use of its processing capacity can be challenging. To address this problem, we propose a new algorithm called Segmented-Flattened-and-Split (SFS) scheduling. SFS schedules high-utilisation tasks in dedicated groups of processors, called clusters, as in federated scheduling, but can also reclaim the processing capacity lost to fragmentation, by splitting the execution of parallel tasks over different existing clusters. Our approach is inspired by semi-partitioned C=D scheduling – an approach originally devised for scheduling non-parallel tasks. We prove that SFS dominates federated scheduling. Furthermore, in experiments with synthetic DAG task sets, it outperforms the best-performing variant of federated scheduling in terms of scheduling success ratio (by up to 49%) and weighted schedulability.

IoT networks require efficient intrusion detection systems that balance detection accuracy with computational constraints for edge deployment. This work introduces a novel packet-level intrusion detection method using 14 statistical features extracted from sliding windows through basic counting operations. The approach operates directly on fixed-size packet windows without requiring flow reconstruction or deep packet inspection to compute statistics. We compare this packet-level method against traditional flow-based feature extraction using tstat on the Edge-IIoTset dataset across 10 attack types. Both approaches train One-Class Support Vector Machine (OCSVM) models for fair evaluation. Results demonstrate that our packet-level method achieves superior detection rates with lower false alarms while significantly reducing feature extraction time compared to traditional flow-based methods.

The Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.

Conventional CAN bus schedulability analysis as-sumes that all messages with a given identifier have the same worst-case length. In this paper we extend that analysis to a more general model in which messages with a given identifier may have different lengths, that vary according to a known periodic pattern. That is, for some positive integer$s$, we assume that the length of message instances$n$and$n+S$with the same id is the same. By leveraging such patterns, where present, our new analysis allows for a more efficient use of CAN bus bandwidth than the application of conventional analysis, which can be pessimistic. This may be interesting when a given node sends the values of multiple signals with different periods. In such a scenario, the conventional CAN schedulability analysis would require either the use of different ids for different signals (assuming there are enough of them), which leads to a higher bandwidth overhead because of the reduplication of message headers, or using only one id, but pessimistically always assuming the maximum possible length of the message, for safety reasons.

The Arrowhead Framework, a SOA-based framework for IoT applications, provides the Event Handler system: a publish/subscribe broker implemented with REST/HTTP(S). However, the existing implementation of the Event Handler suffers from message latency problems that are not acceptable for industrial applications. Thus, this paper describes the refactoring process of this system that enabled it to reach acceptable levels of latency.

Timing analysis of safety-critical real-time embedded systems should be free of both optimistic and pessimistic aspects. The multiframe model was devised to eliminate the pessimism in the schedulability analysis of systems with tasks whose worst-case execution times vary from job to job, according to known patterns. However, this model is optimistic and unsafe for multicores with shared memory controllers, since it ignores memory contention, and existing approaches to stall analysis based on memory regulation are very pessimistic if straightforwardly applied. This paper remedies this by adapting existing stall analyses for memory-regulated systems of conventional Liu-and-Layland tasks to the multiframe model. Experimental evaluations with synthetic task sets (and different task and memory budget assignment heuristics) show up to 85% higher scheduling success ratio for our analysis, compared to the frame-agnostic analysis, enabling higher platform utilisation without compromising safety. We also explore implementation aspects, such as how to speed up the analysis and how to trade off accuracy with tractability.

In mixed-criticality systems, tasks of different criticality share system resources, mainly to reduce cost. Cost is further reduced by using adaptive mode-based scheduling arrangements, such as Vestal’s model, to improve resource efficiency, while guaranteeing schedulability of critical functionality. To simplify safety certification, servers are often used to provide temporal isolation between tasks. In its simplest form, a server is a periodically recurring time window, in which some tasks are scheduled. A server’s computational requirements may greatly vary in different modes, although state-of-the-art techniques and schedulability tests do not allow different budgets to be used by a server in different modes. This results in a single conservative execution budget for all modes, increasing system cost. The goal of this paper is to reduce the cost of mixed-criticality systems through three main contributions: (i) a scheduling arrangement for uniprocessor systems employing fixed-priority scheduling within periodic servers, whose budgets are dynamically adjusted at run-time in the event of a mode change, (ii) a new schedulability analysis for such systems, and (iii) heuristic algorithms for assigning budgets to servers in different modes and ordering the execution of the servers. Experiments with synthetic task sets demonstrate considerable improvements (up to 52.8%) in scheduling success ratio when using dynamic server budgets vs. static “one-size-fits-all-modes” budgets.

Mixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) Vestal model, the existing schedulability analyses are oblivious to memory stalling effects, including stalls from memory bandwidth regulation. This makes it unsafe. In this paper, we address this issue by formulating a schedulability analysis for mixed-criticality fixed-priority-scheduled multicore systems using per-core memory access regulation. We also propose multiple heuristics for memory bandwidth allocation and task-to-core assignment. We implement our analysis and heuristics in a tool and evaluate them, performance-wise, through extensive experiments. Our experiments show that stall-oblivious schedulability analysis may be optimistic due to contention on shared memory resources.

In multicore architectures, there is potential for contention between cores when accessing shared resources, such as system memory. Such contention scenarios are challenging to accurately analyse, from a worst-case timing perspective. One way of making memory contention in multicores more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the number of accesses performed by any given core over time by using periodically replenished per-core budgets. Typically, this assumes that all cores access memory via a single shared memory controller. However, ever-increasing bandwidth requirements have brought about architectures with multiple memory controllers. These control accesses to different memory regions and are potentially shared among all cores. While this presents an opportunity to satisfy bandwidth requirements, existing analysis designed for a single memory controller are no longer safe. This work formulates a worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. This stall analysis can be integrated into the schedulability analysis of systems under fixed-priority partitioned scheduling. Five heuristics for assigning tasks and memory budgets to cores in a stall-cognisant manner are also proposed. We experimentally quantify the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers, and also evaluate the five heuristics for different system characteristics.

Mixed-criticality multicore system design must often guarantee both safety and high performance. Memory bandwidth regulation among different cores can be a useful tool for guaranteeing safety, as it mitigates the interference when accessing main memory. The use of mode changes and system models like Vestal's can help provide both safety, for critical functions, and scheduling performance, by efficiently utilising the platform. This work therefore combines per-core memory access regulation with the well-established Vestal model and improves on the state-of-the-art in two respects: 1) We allow the memory access budgets of the cores to be dynamically adjusted, when the system undergoes a mode change, reflecting the different needs in each mode, for better schedulability. 2) We devise memory-regulation-aware and stall-aware schedulability analysis for such systems, based on AMC-max. By comparison, the state-of-the-art offered no option of dynamic adjustment of core budgets, and only offered regulation-aware schedulability analysis based on AMC-rtb, which is inherently more pessimistic. Finally, 3) we consider different task assignment and bandwidth allocation heuristics, to assess the improvement from the dynamic memory budgets and new analysis. Our results show improvements in schedulability ratio of up to 9.1% over the state-of-the-art.

The design of mixed-criticality systems often involves painful tradeoffs between safety guarantees and performance. However, the use of more detailed architectural models in the design and analysis of scheduling arrangements for mixed-criticality systems can provide greater confidence in the analysis, but also opportunities for better performance. Motivated by this view, we propose an extension of Vestal's model for mixed-criticality multicore systems that (i) accounts for the per-task partitioning of the last-level cache and (ii) supports the dynamic reassignment, for better schedulability, of cache portions initially reserved for lower-criticality tasks to the higher-criticality tasks, when the system switches to high-criticality mode. To this model, we apply partitioned EDF scheduling with Ekberg and Yi's deadline-scaling technique. Our schedulability analysis and scalefactor calculation is cognisant of the cache resources assigned to each task, by using WCET estimates that take into account these resources. It is hence able to leverage the dynamic reconfiguration of the cache partitioning, at mode change, for better performance, in terms of provable schedulability. We also propose heuristics for partitioning the cache in low- and high-criticality mode, that promote schedulability. Our experiments with synthetic task sets, indicate tangible improvements in schedulability compared to a baseline cache-aware arrangement where there is no redistribution of cache resources from low- to high-criticality tasks in the event of a mode change.

Schedulability analyses, while valuable in theoretical research, cannot be used in practice to reason about the timing behaviour of a real-time system without including the overheads induced by the implementation of the scheduling algorithm. In this paper, we provide an overhead-aware schedulability analysis based on demand bound functions for two hard real-time semi-partitioned scheduling algorithms, EDF-WM and C=D. This analysis is based on a novel implementation that uses a global clock to reduce the overheads incurred due to the release jitter of migrating subtasks. The analysis is used to guide the respective off-line task assignment and splitting procedures. Finally, results of an evaluation are provided highlighting how the different algorithms perform with and without a consideration of overheads.

We present Carousel-EDF, a new hierarchical scheduling algorithm for a system of identical processors, and its overhead-aware schedulability analysis based on demand bound functions. Carousel-EDF is an offshoot of NPS-F and preserves its utilization bounds, which are the highest among algorithms not based on a single dispatching queue and that have few preemptions. Furthermore, with respect to NPS-F, Carousel-EDF reduces by up to 50% the number of context switches and of preemptions caused by the high-level scheduler itself. The schedulability analysis we present in this paper is grounded on a prototype implementation of Carousel-EDF that uses a new implementation technique for the release of periodic tasks. This technique reduces the pessimism of the schedulability analysis presented and can be applied, with similar benefits, to other scheduling algorithms such as NPS-F.

Wireless Mesh Networks (WMNs) are a promising communication technology that may offer greater flexibility and reliability, when compared to traditional wireless networks. WMNs open up new applications domains, but still need to find efficient mechanisms to deal with scalability and timeliness requirements. This paper proposes a scheme for Path Selection and Message Forwarding in IEEE 802.11s networks, that is suitable to be used in industrial environments. We present the DHT-based Cluster Routing Protocol (DCRP), a routing protocol based on DHTs, clustering of nodes and use of proxies. DCRP allows to improve the overall network performance by reducing the time required for path selection and the number of communication hops in large sized networks.

We present a family of reliable broadcast protocols designed to take advantage of the dual scheduling TDMA (DuST) scheme provided by current state-of-the-art automotive control networks such as FlexRay. These protocols are a complement to FlexRay's native communication services, which do not provide sufficient fault tolerance for safety-critical applications. A reliability evaluation of the proposed protocols carried out with the help of the probabilistic model checker PRISM shows that the proposed protocols can achieve reliability levels suitable for safety-critical applications.

Keeping up with the timing constraints of real-time traffic in wireless environments is a hard task. One of the reasons is that the real-time stations have to share the same communication medium with stations that are out of the sphere-of control of the real-time architecture. That is, with stations that generate timing unconstrained traffic. The VTP-CSMA architecture targets this problem in IEEE 802.11 wireless networks. It is based on a Virtual Token Passing procedure (VTP) that circulates a virtual token among real-time stations, enabling the coexistence of real-time and non realtime stations in a shared communication environment. The worst-case timing analysis of the VTP-CSMA mechanism shows that the token rotation time is upper-bounded, even when the communication medium is shared with timing unconstrained stations. Additionally, the simulation analysis shows that the token rotation mechanism behaves adequately, even in the presence of error-prone communication channels. Therefore, the VTP-CSMA architecture enables the support of real-time communication in shared communication environments, without the need to control the timing behavior of every communicating device. A ring management procedure for the VTP-CSMA architecture is also proposed, allowing real-time stations to adequately join/leave the virtual ring. This ring management procedure is mandatory for dynamic operating scenarios, such as those found in VoIP applications.