EDBT 2026 Demo / reviewers in the wild / expert
Robert E. Thomas
dblp:47/2255
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Optical networks · 92% Routing and switching · 8% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 61% Parallel and multicore computing · 30% Performance modeling and evaluation · 9% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Optical networks
all-optical networks |
0.0 | 1 | 1996 | A Wideband All-Optical WDM Network (Invited Paper) · IEEE J. Sel. Areas Commun. 1996 |
Optical networks › wavelength-routed network
wavelength routing |
0.0 | 1 | 1996 | A Wideband All-Optical WDM Network (Invited Paper) · IEEE J. Sel. Areas Commun. 1996 |
Optical networks
WDM networks |
0.0 | 1 | 1996 | A Wideband All-Optical WDM Network (Invited Paper) · IEEE J. Sel. Areas Commun. 1996 |
Routing and switching
circuit switching |
0.0 | 1 | 1996 | A Wideband All-Optical WDM Network (Invited Paper) · IEEE J. Sel. Areas Commun. 1996 |
Optical networks
optical network architecture |
0.0 | 1 | 1996 | A Wideband All-Optical WDM Network (Invited Paper) · IEEE J. Sel. Areas Commun. 1996 |
Processor architecture and microarchitecture
dataflow architecture |
0.0 | 1 | 1980 | Performance of a Simulated Dataflow Computer · IEEE Trans. Computers 1980 |
Parallel and multicore computing
dataflow computing |
0.0 | 1 | 1980 | Performance of a Simulated Dataflow Computer · IEEE Trans. Computers 1980 |
Processor architecture and microarchitecture › dataflow architecture
dataflow machine |
0.0 | 1 | 1980 | Performance of a Simulated Dataflow Computer · IEEE Trans. Computers 1980 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1980 | Performance of a Simulated Dataflow Computer · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
wavelength partitioning · 0.0flow analysis · 0.0dataflow programming language · 0.0complexity analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | A Wideband All-Optical WDM Network (Invited Paper)abstractWe describe some of the results of the Advanced Research Projects Agency (ARPA) sponsored Consortium on Wideband All-Optical Networks in developing architectures, technology components, and applications for the realization of scaleable, wideband, and transparent optical wavelength-division multiplexing (WDM) networks. Our architecture addresses all-optical transport over the wide, metropolitan, and local areas. It utilizes wavelength partitioning, routing, and active multiwavelength cross-connect switches to achieve a network that is scaleable in the number of users, data rates, and geographic span. The network supports two services which can be point-to-multipoint or multipoint-to-multipoint simplex or duplex connections. The A service is a transparent physically circuit-switched service and the B-service is a scheduled time-slotted circuit which is transparent within its time slots. We have developed a 20-channel local and metropolitan area WDM testbed deployed in the Boston area, now undergoing characterization and experimental applications. Ivan P. Kaminow, Chris R. Doerr, Corrado Dragone, Tom Koch, Uzi Koren, Adel A. M. Saleh, Alan J. Kirby, Cüneyt M. Özveren, B. Schofield, Robert E. Thomas, Richard A. Barry, Daniel M. Castagnozzi, Vincent W. S. Chan, B. Roe Hemenway Jr., Douglas Marquis, Salil A. Parikh, Mark L. Stevens, Eric A. Swanson, Steven G. Finn, Robert G. Gallager |
IEEE J. Sel. Areas Commun. | 10 |
| 1980 | Performance of a Simulated Dataflow ComputerabstractOur goal is to devise a computer comprising large numbers of cooperating processors (LSI). In doing so we reject the sequential and memory cell semantics of the von Neumann model, and instead adopt the asynchronous and functional semantics of dataflow. We briefly describe the high-level dataflow programming language Id, as well as an initial design for a dataflow machine and the results of detailed deterministic simulation experiments on a part of that machine. For example, we show that a dataflow machine can automatically unfold the nested loops of n X n matrix multiply to reduce its time complexity from 0(n3) to 0(n) so long as sufficient processors and communication capacity is available. Similarly, quicksort executes with average 0(n) time demanding 0(n) processors. Also discussed are the use of processor and communication time complexity analysis and "flow analysis," as aids in understanding the behavior of the machine. Kim P. Gostelow, Robert E. Thomas |
IEEE Trans. Computers | 2 |