Haiqiong Yao

dblp:47/2431 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Software engineering, system software, and programming languages
1 paper
Program verification · 100%
Theoretical computer science
1 paper
Automated reasoning and model checking · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › formal verification
abstraction refinement
0.112010
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement · IEEE Trans. Computers 2010
Electronic design automation › hardware verification and test
hardware verification
0.112010
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement · IEEE Trans. Computers 2010
Electronic design automation
model checking
0.112010
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement · IEEE Trans. Computers 2010
Program verification › refinement
interface refinement
0.112009
Automated Interface Refinement for Compositional Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Program verification
modular verification
0.112009
Automated Interface Refinement for Compositional Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009
Electronic design automation › hardware verification and test › hardware verification › circuit-level verification
asynchronous circuit verification
0.012010
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement · IEEE Trans. Computers 2010
Automated reasoning and model checking › model checking
state space reduction
0.012009
Automated Interface Refinement for Compositional Verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009

Methods — techniques the papers use, named apart from their topics

state space reduction · 0.3overapproximation · 0.1over-approximation · 0.1
YearPublicationVenuePosition
2010 Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement
abstract
Divide-and-conquer is essential to address state explosion in model checking. Verifying each individual component in a system, in isolation, efficiently requires an appropriate context, which traditionally is obtained by hand. This paper presents an efficient modular model checking approach for asynchronous design verification. It is equipped with a novel abstraction refinement method that can refine a component abstraction to be accurate enough for successful verification. It is fully automated, and eliminates the need of finding an accurate context when verifying each individual component, although such a context is still highly desirable. This method is also enhanced with additional state space reduction techniques. The experiments on several nontrivial asynchronous designs show that this method efficiently removes impossible behaviors from each component including ones violating correctness requirements.
Hao Zheng 0001, Haiqiong Yao, Tomohiro Yoneda
IEEE Trans. Computers2
2009 Automated Interface Refinement for Compositional Verification
abstract
Compositional verification is essential for verifying large systems. However, approximate environments are needed when verifying the constituent modules in a system. Effective compositional verification requires finding a simple but accurate overapproximate environment for each module. Otherwise, many verification failures may be produced, therefore incurring high computational penalty for distinguishing the false failures from the real ones. This paper presents an automated method to refine the state space of each module within an overapproximate environment. This method is sound as long as an overapproximate environment is found for each module at the beginning of the verification process, and it has less restrictions on system partitioning. It is also coupled with several state-space reduction techniques for better results. Experiments of this method on several large asynchronous designs show promising results.
Haiqiong Yao, Hao Zheng 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1