Test data collection for a failing integrated circuit (IC) can be very expensive and time consuming. Many companies now collect a fix amount of test data regardless of the failure characteristics. As a result, limited data collection could lead to inaccurate diagnosis, while an excessive amount increases the cost not only in terms of unnecessary test data collection but also increased cost for test execution and data-storage. In this work, the objective is to develop a method for predicting the precise amount of test data necessary to produce an accurate diagnosis. By analyzing the failing outputs of an IC during its actual test, the developed method dynamically determines which failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. The method leverages several statistical learning techniques, and is evaluated using actual data from a population of failing chips and five standard benchmarks. Experiments demonstrate that test-data collection can be reduced by > 30% (as compared to collecting the full-failure response) while at the same time ensuring >90% diagnosis accuracy. Prematurely terminating test-data collection at fixed levels (e.g., 100 failing bits) is also shown to negatively impact diagnosis accuracy.

This paper describes a method for improving the test quality of digital circuits on a per-design basis by: 1) monitoring the defect behaviors that occur through volume diagnosis; and 2) changing the test patterns to match the identified behaviors. To characterize the behavior of a defect (i.e., the conditions when a defect is activated), physically-aware diagnosis is employed to extract the set of signal lines relevant to defect activation. Then, based on the set of signal lines derived, the defect is attributed to one of several behavior categories. Our defect level model uses the behavior-attribution results of the current failing population to guide test-set customization to minimize defect level for a given constraint on test costs, or alternatively, ensure that defect level does not exceed some predetermined threshold. Circuit-level simulation involving various types of defects shows that defect level can be reduced by 30% using this method. Simulation experiment on actual chips also demonstrates quality improvement.

Logic diagnosis analyzes the observed failing circuit responses to derive the potential defect sites. This paper describes a method for improving diagnosis through failing behavior identification (FBI). FBI captures defect behavior (i.e., activation conditions of the defect) by identifying the signal lines related to defect activation. This additional information allows the root cause to be estimated in order to improve yield, design quality, and test quality, as well as guide PFA to perform faster defect localization. FBI is accomplished by: 1) deriving the neighborhood states of the defect site, i.e., the actual values on the signal lines within logical or physical proximity to the defect site, and 2) identifying the signal lines that are most relevant to defect activation. The efficacy of FBI is validated using circuit-level and logic-level simulation experiments. The results show that FBI achieves an average accuracy of 94% in identifying signal lines that are relevant to defect activation, a 28% improvement over an existing approach. Moreover, by analyzing the neighborhood states of each defect site reported by logic diagnosis, sites that are not likely to be defective can be eliminated, which leads to improvement in diagnosis resolution. Experiment results show that with little influence on diagnosis accuracy, the number of incorrect defective sites reported by logic diagnosis can be reduced by 64%, on average.

At substantial cost, conventional methods for evaluating test quality apply a specially-generated test set to a large population of manufactured chips. In contrast, a new time-efficient framework for evaluating test quality (FETQ) that uses tester data from normal production has been developed and validated. FETQ estimates the quality of both static and adaptive test metrics, where the latter guides test using the results of statistical data analysis. FETQ is innovative since instead of evaluating a single measure of effectiveness (e.g., number of unique defects detected), it provides a confidence interval of effectiveness based on the analysis of a collection of test sets. FETQ is demonstrated by measuring the chip-detection capability of several static and adaptive test metrics using tester data from actual ICs.

We propose a methodology that effectively estimates the defect-type distribution that affects a design fabricated in a given manufacturing process. Understanding the distribution can improve design quality, test quality, and the manufacturing process itself. The methodology is composed of i) an improved approach for identifying the signal lines relevant to defect activation at each site reported by diagnosis, ii) a new behavior attribution method, and iii) a novel approach to estimate the defect-type distribution. The efficacy of this methodology is validated using circuit-level simulation experiments. The results show that the method achieves an average accuracy of 94% in identifying signal lines that are relevant to the activation of a defect. When estimating defect-type distribution for a population affected by a variety of defects, the average estimation accuracy is 92% with ideal diagnosis. With a realistic diagnosis (i.e., the inherent ambiguity of diagnosis is accounted for), the estimated defect-type distribution is 85% accurate, on average.

This paper describes a multiple-defect diagnosis methodology that is flexible in handling various defect behaviors and arbitrary failing pattern characteristics. Unlike some other approaches, the search space of the diagnosis method does not grow exponentially with the number of defects. Results from extensive simulation experiments and real failing integrated circuits show that this method can effectively diagnose circuits that are affected by a large (>20) or small number of defects of various types. Moreover, this method is capable of accurately estimating the number of defective sites in the failing circuit.

We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

We propose an effective multiple defect diagnosis methodology that does not depend on failing pattern characteristics. The methodology consists of a conservative defect site identification and elimination algorithm, and an innovative path-based defect site elimination technique. The search space of the diagnosis method does not grow exponentially with the number of defects in the circuit under diagnosis. Simulation experiments show that this method can effectively diagnose circuits that are affected by 10 or more faults that include multiple stuck-at, bridge and transistor stuck-open faults.

A multiple defect diagnosis methodology consisting of a defect site identification and elimination method, a path-based defect site elimination method, and a defect site selection and ranking method is described. The flexibility of the diagnosis method in handling various defect behaviors and arbitrary failing pattern characteristics is demonstrated through extensive simulations. Unlike some competing approaches, the search space of the diagnosis method does not grow exponentially with the number of defects. Results from over 1700 simulated and 131 failing ICs show that this method can effectively diagnose circuits that are affected by a large (>20) or small number of defects of various types. Specifically, when diagnosing circuits with more than 20 defects, our method identifies 65% of them, and the number of sites reported per actual defective site is, on average, 1.17. For circuits affected by two defects, these numbers change to 86% and 1.85, respectively. Finally, 84% of our top-ranked sites are actual defect sites.