This paper presents the design of a fully flexible temperature sensor for wearable applications. The sensor is implemented using the newly available flexible integrated electronic circuit (Flex-IC) technology from Pragmatic Semiconductor [1]. To address the design challenges due to the limited set of thin film components available in this non-CMOS technology, a counter-based time-to-digital conversion (TDC) technique has been developed, where the pulses provided by a temperature-dependent ring oscillator are gated and counted by a temperature-independent delay cell. The operation of the delay cell relies on the temperature coefficient cancellation of resistive components by a cross-coupled pair. A tunable calibration mechanism is also incorporated in the design to handle the process corners in a temperature range of 32 °C - 42 °C suitable for biological sensing. The presented sensor design exhibits a low time-jitter induced measurement error, with a 0.81 % probability of toggling the least significant bit (LSB) per sample, maintaining 0.1 °C precision and a zero-error range of 6.8 °C, while dissipating a power of 2.5 mW with an acquisition time of 3 ms. The chip layout measures 3.0 mm×3.0 mm with a die thickness of 30 μm. Compared to existing rigid and hybrid systems, the Flex-IC technology opens up opportunities for advancing conformal electronics, particularly for applications requiring continuous monitoring on dynamic body surfaces.

This paper proposes a new curriculum for under-graduate students that teaches chip-level design and assembly for developing a complete, tapeout-ready System-on-Chip (SoC) that includes synthesized digital components, analog/mixed-signal blocks, and IP such as memories and I/O drivers. The course will guide students through the process of synthesizing RTL into layout blocks, floor planning, chip-level routing of components, simulation, verification, and tapeout using a 45 nm public-domain PDK. By the end of the class, students will be capable of designing a complete, verified, and tapeout-ready SoC containing complex digital microcontroller circuitry and analog/mixed-signal front-ends. The course will take students through the steps to design and assemble a chip based on an existing SoC designed at the authors’ university. This will lead to the development of a workforce capable of designing mixed-signal SoC solutions for broader industrial and academic needs.

This work presents a single-chip electronics interface for low power, high count rate gamma ray spectroscopy using a novel current nulling scheme that reduces power consumption to 8.8 mW at a count rate of 30 kcps. The current nulling circuit monitors and subtracts the time-varying PMT anode bias network current that would normally lead to a significant integration error at high count rates. This allows the use of low power, event-driven circuit topologies downstream at higher count rates than would otherwise be supported. With this method, the detection resolution degradation improves from 0.85%70/kcps to 0.02%/kcps and the spectrum shift is reduced from −22bins/kcps to 0.32 bins/kcps.

Electronic skin (e-skin) interface building blocks are presented that are suitable for integration with array-based tactile sensors for prosthetic applications. The first is a low power, low noise capacitive transimpedance amplifier (CTIA) compatible with charge-based polyvinylidene fluoride (PVDF) sensors. The second is a high efficiency RISC-V microcontroller unit (MCU) with a custom, on-chip neural processing unit (NPU) to accelerate gesture recognition tasks. Two test chips have been fabricated using a 65 nm CMOS technology: one for the prototype analog front-end (AFE) including the CTIA, and the other for the MCU and NPU. The AFE consumes 112.5 nW per channel, and the MCU consumes 2.83 mW while running the NPU at 112 MHz.

A standalone radiation detection and identification system is designed and tested which quantizes gamma ray energies with a scintillator, photomultiplier tube, and a custom multichannel analyzer chip to construct a gamma ray energy histogram. The histogram is used as the input to a fast, low memory, versatile neural network that runs in software on a microcontroller and identifies in real time which radioisotopes are present in the radiation source. The neural network accurately identifies the radioisotopes for which it has been trained, running in under 91.4 ms, consuming less than 6.2 kB of memory, and expending 274 μJ of energy each time it is executed.

A low-power, single-chip electronic skin interface is presented. Its small size and reduced battery requirements are ideal for advanced prosthetic limbs that utilize electronic skin to provide their user tactile feedback. The architecture consists of multiple charge-sensitive analog front ends (AFEs) interfaced to a central, 16-bit microcontroller core which is capable of processing the sensory information in real-time. Event-driven operation allows the chip to monitor all input channels while idle and consuming minimal energy. A test chip has been fabricated in a 0.13 μm CMOS technology and implements 13 AFE channels. Its functionality is demonstrated by interfacing the chip to a prototype electronic skin based on polyvinylidene fluoride (PVDF) piezoelectric sensors. Signals from the sensors are captured by the presented chip and processed to calculate the corresponding charge. This is accomplished by programming the microcontroller with a custom software algorithm implemented in C, granting the system the flexibility to interface to different types of sensors. The single-chip electronic skin system consumes 7.0 μW per channel and 76.5 μW in the example application, making it suitable for use with battery-powered prosthetics.

This paper presents the design and test results of a low-power radiation detection system. When paired with a scintillation-based detector, the design forms a compact, portable unit suitable for use in long-duration radiation monitoring applications. The system consists of two distinct modules. The first is a low-power detector power supply (DPS) used to generate multiple high voltages necessary to bias a photomultiplier tube (PMT), which is controlled and regulated by a 0.35 μm controller chip. The second is a 0.13 μm low-power multichannel analyzer (MCA) chip with an integrated microcontroller and event-driven charge-sensitive front-ends with 10-bit ADCs used to acquire and analyze the energy spectrum of the radiation. The MCA interfaces with the DPS through a digital interface, allowing it to tune the PMT voltage to compensate for temperature and time variations in the detector. Both modules were fabricated and tested to verify low-power functionality, consuming 2.4 mW when sensing radiation events at 1000 counts/sec (cps).

This work presents a smart camera application of real-time trajectory calculation, utilizing a neighborhood-level parallel processing vision chip to track objects and predict their path of motion. The vision chip contains arrays of pixel elements embedded into neighborhood processors, which are tiled to create a 64×80 resolution vision chip. The high frame rate and processing speed of the vision chip allows for calculation of the object's trajectory before leaving the frame. Algorithm design for the tracking algorithm is discussed and hardware test results for linear and non-linear path predictions are presented. Further considerations in optimizing the algorithm for higher precision and robust trajectory forecasting are discussed.

This paper presents the design and test results of a low-power 10-bit multichannel analyzer (MCA) chip for radiation detection. A low-power and event driven charge sensitive front-end and analog-to-digital converter (ADC) are implemented together with a microcontroller on a single chip. This level of integration leads to a compact MCA that can process and build pulse height spectra when interfaced with a range of scintillator detectors, with the ability to digitally process the spectra using software running as embedded code. The design was fabricated in a 0.13 μm CMOS technology and tested to validate the approaches taken. The measured power consumption of the MCA is below 85 μW while detecting multiple radioisotopes.

This live demonstration features a vision chip based on a neighborhood level parallel processing paradigm. Processors are physically embedded within groups of pixels, complete with memory and algorithmic capabilities controlled by a custom instruction set. This results in a scalable resolution, parallel processing vision chip with flexible programmability that can perform a wide variety of image and video processing tasks. A prototype vision chip has been fabricated in a 0.13μm CMOS technology consisting of an 8×10 array of processors with a 64×80 resolution. The setup demonstrates how the vision chip can execute various parallel processing programs and manipulate image acquisition parameters to match the requirements of a scene in real-time.

This paper presents a novel vision chip architecture based on pixel-neighborhood level parallel processing. The architecture consists of neighborhoods of 8×8 digital pixel sensors, where each group of 8×8 sensors is physically embedded within its own neighborhood processing core on the same focal plane. To that end, a low complexity neighborhood processor architecture along with a general-purpose, 8-bit instruction set has been designed and implemented. This allows program execution to be carried out in parallel on a two-dimensional array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution. A prototype vision chip housing an array of 8×10 neighborhoods with a 64×80 resolution has been designed and fabricated in a 0.13 μm fabrication process. The single-chip vision system can be programmed to perform a variety of image and video processing tasks. A number of image processing tasks are presented to demonstrate the functionality of pixel-neighborhood level parallelism.

This paper presents the design of an Analog-to-Information spectral decomposition scheme suitable for parallel low-power analog and mixed-signal VLSI implementation. The novel scheme extracts sufficient information to achieve good back-end signal detection and classification performance while using less power than purely digital spectral techniques such as FFT. Simulations of a prototype system in a mixed-signal 130nm CMOS process show a feasible solution space given an on-line self-calibrating system.

In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops and thereby reduces power consumption. A test chip is designed and fabricated in a 0.5 μm CMOS technology to verify the power saving properties of the architecture.

This paper presents the design and test results of a computational radiation sensor system based on a single chip solution that can perform standalone gamma isotope identification. A low power sensor front end with a charge sensitive amplifier, an event driven analog-to-digital converter, and a dedicated microcontroller are integrated on the same chip to process and bin the isotope data from a NaI gamma ray detector according to gathered pulse height. This combination effectively implements a single chip multichannel analyzer with the capability to do further processing of the data in software. To that end, a compact fixed-point program was developed to further analyze the pulse height spectra gathered from a variety of gamma ray sources and perform on-chip real-time gamma isotope identification. The design was fabricated in a 0.18 μm CMOS technology with field tests demonstrating the validity of the approaches taken. The total computational sensor system power consumption is less than 30 μW, excluding the detector power consumption. The gamma isotope identification program executes in 70 ms.

The design of an ultra-low power buck regulator is proposed. The regulator is designed to be integrated with a single-chip wireless sensor network and provide high efficiency at low output currents to maximize the sensor's battery life. The maximum output current is 50 mA. Dynamic voltage scaling is also supported to further reduce total power dissipation. The no-load current of the complete regulator is less than 1 muA. Simulation results give an expected efficiency of over 80% at 20 muW of output power and a peak efficiency of over 95%.

The design of the baseband processor for a non-coherent ultra-wideband receiver is presented. The design integrates all functions necessary for a stand-alone UWB receiver including packet detection and symbol synchronization. The design does not require any high-speed ADCs, but instead relies on simple circuits in the analog domain to acquire the packet and track the incoming data stream. The design provides extensive feedback to the host system about channel conditions and signal strength. The design has been implemented in a 0.18 [m process with a baseband power consumption of 3.5 mW.

This paper presents the design and testing results of a computational radiation sensor. The design utilizes a dedicated microcontroller to perform computation and data aggregation on the sensor head to reduce the information bit rate. A low-power charge sensitive amplifier and ADC complete the design. The design was implemented in a 0.35 µm CMOS technology with field tests demonstrating the validity of the approaches taken.

This paper presents the design and measurements of a predictive coding on-sensor compression CMOS imager. Predictive coding is employed to decorrelate the image. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit. The decorrelated image is encoded with a bank of column-parallel entropy encoders. Each encoder is combined with a single-slope analog-to-digital converter (ADC) to reduce area complexity and power consumption. The area savings resulting from such combination allow to integrate an ADC and an entropy encoder at the column level. A prototype chip was fabricated in a 0.35 μm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm × 5.96 mm which includes an 80 × 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

In this paper, a focal plane SPIHT image compression scheme has been integrated on the focal plane of CMOS image sensor. A test chip is prototyped in 0.35μm technology to verify the design. In our image compression scheme, focal plane prediction replaces the traditional wavelet transform for image decomposition, and the traditional SPIHT coding is modified to reduce computational complexity and to suit the parallel implementation on the sensor focal plane. Simulated compression performance is still good, especially at low bit rates, compared to traditional SPIHT and other compression schemes. Integrating SPIHT compression on the focal plane not only reduces the sensor readout volume, but also provides all the advantages of SPIHT compression including both high image quality and optimized data ordering for progressive image transmission.

A complete low-power front end for particle detection applications is proposed. The front end integrates a charge sensitive amplifier with a novel adaptive biasing scheme which allows the DC bias currents to be scaled below conventional limits. A peak detector circuit obtains a peak value for each detection event which is then converted to digital via an 8 bit charge-redistribution successive approximation analog to digital converter. The ADC is shut off in between detection events to further reduce power consumption. The entire circuit consumes between 39muW and 400muW of power depending on the particle detection rate. This low power operation enables the development of compact, long-life, battery powered, remote particle sensors.

A stand-alone design automation tool tailored for RF CMOS LNA design is presented. Rather than relying on commercially available circuit simulators such asSpectreorHspice, the presented synthesis tool is self-contained with its own built-in modules for faster performance evaluation. Silicon- verified RF device models are incorporated into the synthesis procedure for accurate parasitic modeling. To validate the proposed approach, an LNA circuit operating at 900 MHz is synthesized and fabricated in a 0.25 mum CMOS technology. Measurement results are presented which shows the viability of the proposed synthesis tool.

A stand-alone design automation tool tailored for radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) low-noise amplifier (LNA) designs is presented. Rather than relying on commercially available circuit simulators such as Spectre or Hspice, the presented synthesis tool is self-contained with its own built-in modules for faster optimization. Foundry-provided silicon-verified RF device models are incorporated into the synthesis procedure for accurate parasitic modeling. The proposed synthesis tool can be used as an independent circuit design environment for LNAs or, alternatively, as an auxiliary tool generating an initial design for a commercial design environment to reduce design time. To validate the proposed approach, an LNA operating at 900 MHz is synthesized and fabricated in a 0.25-mum CMOS technology. Measurement results are presented, which shows the viability of the proposed synthesis tool.

A CMOS image sensor has been designed to perform the front-end image decomposition in a prediction-SPIHT image compression scheme. The prediction circuitry based on charge sharing is integrated inside the sensor array to perform 3-level image decomposition. A CMOS test chip has been prototyped and tested. The test results justify the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate but with much less data readout volume. Also, the sensor can be used to achieve comparable compression performance with much lower computational complexity compared to 2D discrete wavelet transform (DWT) based image compression.

A previously implemented CNN layer based on a bio-inspired system model is integrated with optical sensors comprised of PN type photodiodes and the design is fabricated in CMOS technology. The implemented test chip is measured and obtained results are presented. The sensor integration marks a new step in prototyping of this system in CMOS, which allows the cell states to be programmed via light interactions, rather than successive state programming procedure which was utilized previously. It is shown that the cell input states in the network can be successfully introduced via exposure of the 2D array to a light source. The followed custom design methods and this remarkably compatible sensor integration can lead to compact on-chip solutions for real-time high performance applications, including but not limited to certain types of image processing.

A focal plane video compression integrated circuit is presented. The design consists of a 128 times 128 pixel array and a bank of column-level processors. Each one of the column-level processors performs the tasks of image decorrelation, quantization, and entropy encoding. The chip provides at its output a compressed bit stream. The integration of the quantizer and the entropy encoder at the column level is possible by sharing circuitry between a single-slope analog-to-digital converter and a Golomb-Rice entropy encoder. In addition, the design includes a low-complexity algorithm for the adaptation of the Golomb-Rice coder to the statistics of the video signal. The design has been fully verified through simulations and has been implemented in a 0.35 mum CMOS technology. The chip layout occupies an area of 7 times 5 mm2

We present a CMOS image sensor that performs focal plane image decomposition based on charge sharing computation circuitry. The effect of parasitic capacitance between capacitor bottom plate and substrate on the computational accuracy is discussed and a new circuit is also proposed to characterize the parasitic effects. The test results demonstrate that prediction based focal plane image compression can be realized inside the sensor array resulting in high compression performance using frame rate pixel parallel computation. This architecture can subsequently be combined with backend level testing encoding to form a complete compression sensor.

Ultra wideband (UWB) systems provide high data rates for wireless systems but are also challenged by high power, narrowband interferers falling within the band of interest. This paper proposes an RF front-end implementation to adaptively remove a narrowband, high power interferer from a UWB signal. These signals can drive front-end electronics into saturation, resulting in the loss of the UWB signal. The system is based on an analog implementation of the LMS algorithm. In this study two antenna sensors and analog signal processing are utilized to remove one interferer. This can be extended to more interferers when utilizing additional antenna elements. As opposed to varactor diode based notch filters, this filter implementation achieves wide tuning ranges and can be fully integrated in CMOS. Matlab simulations show that the impact of the adaptive interferer removal on the UWB band can be limited to a narrow frequency band preserving most of the UWB signal power.

In this paper, a hand-held neutron radiation sensor application is described. The sensor system utilizes a new class of boron-carbide diode that interacts with incoming neutrons. To interface with the boron-carbide diode an integrated front-end is designed in a 1.5/spl mu/m standard CMOS technology. With the diode and front-end microchip, a hand-held neutron detection system was realized with an embedded microcontroller for realtime processing. The hand-held detector operation was then tested with a plutonium-beryllium neutron source. Testing results confirm the validity of the approach and the functionality of the design.

An automatic synthesis tool for RFIC design is demonstrated. The tool incorporates built-in numerical simulators for fast evaluation of the performance metrics. Nonlinearity is modeled using Volterra series method. The tool additionally provides the dimensions of the on-chip inductors along with their values. To validate this approach, a low noise amplifier (LNA) at 900MHz is synthesized using a 0.35mum CMOS process. The synthesis results are verified with the simulation data, obtained from Cadence SPECTRE circuit simulator

A bio-inspired MOS cell design, which can be used in reaction-diffusion systems, and the corresponding implementation of a test reaction-diffusion CNN (RD-CNN) layer is presented. The network architecture and an approximate analysis of its certain D.C. characteristics are given. A test chip, which includes an array of the connected cells, is implemented. The chip also has separate test cells, which employ thick oxide MOSFET. The wave propagation in the network and I-V characteristics of the cells using thick-oxide MOSFETs are demonstrated and verified with measured results. The cell circuits and the resulting network are very compact and easily implementable with available technologies.

This paper presents an analog integrated circuit synthesis system based on an evolutionary approach. The system contains several novel features. One of these is the high-performance optimization algorithm, which is a combination of evolutionary strategies and simulated annealing. Modeling of dc parameters is done via a fast dc simulator developed for this purpose whereas modeling of ac parameters can be done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. This way, the optimized circuit becomes tolerant to process variations. The synthesis system has been tested on several independent examples and synthesized circuits have been verified functionally with SPICE simulations. Finally, a prototype chip composed of the three examples has been manufactured. The measurement results have demonstrated the validity of the synthesis system on silicon.

In this paper, an evolution-based approach to design of neural fuzzy networks is presented. The proposed strategy optimizes the whole fuzzy system with minimum rule number according to given specifications, while training the network parameters. The approach relies on an optimization tool, which combines evolution strategies and simulated annealing algorithms in finding the global optimum solution. The optimization variables include membership function parameters and rule numbers which are combined with genetic parameters to create diversity in the search space due to self-adaptation. The optimization technique is independent of the topology under consideration and capable of handling any type of membership function. The algorithmic details of the optimization methodology are discussed in detail, and the generality of the approach is illustrated by different examples.

A GRBF network is designed for VLSI implementation. Building blocks of the network consist mainly of analog circuits: op amp, multiplier, multiplying DAC (digital to analog converter), floating resistor, summer and exponentiator. Parameters of the network (center, width of the Gaussian function and output layer weights) are represented digitally for convenient interfacing. It is shown that individual GRBF units allow independent tuning of center, width and amplitude. Several network structures are simulated as function approximation examples, and the performance is verified to be satisfactory.

This paper describes numerical integration algorithms based upon Bezier splines. Numerical integration in the context of circuit simulation takes place in the transient analysis portion of the circuit simulators. The solution to the differential-algebraic equation system describing a dynamic circuit is obtained by formulas which formulate the solution as a Bezier function. The algorithms presented in this paper are fully investigated and developed for analog circuit simulation. SPICE program is used in testing these algorithms. Test circuit simulation results are provided to display the performance of the algorithms.>