This paper introduces SARA, a semantic-assisted reinforced active learning framework for enhancing entity alignment (EA) under limited supervision scenarios. SARA addresses the challenges of EA in real-world scenarios, including knowledge graph heterogeneity and limited training ground truth. SARA effectively selects valuable entity pairs with limited labeled data by combining reinforced active learning and semantic information. It utilizes a pair-wise language model based on Sentence-BERT to learn informative name embeddings that capture entity name semantics. These embeddings are combined with structural embeddings and trained using a novel semantic-assisted alignment loss. Extensive experiments on benchmark datasets and a real-world dataset demonstrate the superiority of SARA over existing approaches, particularly in limited labeled data scenarios. The paper also provides insights into fine-tuning strategies, presents ablation studies, and conducts sensitivity analyses to validate the effectiveness of SARA.

For processor cores embedded in mission-critical devices, post-deployment self-testing is mandatory for reliability assurance. One promising solution to processor self-testing is software-based self-test (SBST). The idea is for the processor under test to execute self-test programs that are tailored to activate faults and observe test responses. This paper proposes a hybrid approach that utilizes justification techniques and test program templates to convert ATPG patterns to self-test programs. First, we develop a BDD-based justification engine which enables test program optimization for fault detection. To reduce the justification complexity, a test program template is used to control and observe general purpose registers; to address the difficulty of BDD construction, circuit partitioning based heuristics are developed. Furthermore, we design a customized test program template for the register file circuit to reduce the test program generation time and improve fault coverage. The proposed techniques are validated on a RISC-V processor and achieve 90.4% transition delay fault coverage—a 4% improvement over our previous template-based approach.

As the design complexity grows dramatically in modern circuit designs, 2.5D/3D heterogeneous integration (HI) becomes effective for system performance, power, and cost optimization, providing promising solutions to the increasing cost of more-Moore scaling. In this talk, we investigate the chip, package, and board co-design methodology with advanced packages and optical communication considering essential issues on physical design, electrical, thermal, and mechanical effects, timing, and testing, and suggest future research opportunities. Layout: A robust and vertically integrated physical design flow for HI design is needed. We address chip-, package-, and board-level component planning, package-level RDL routing, board-level routing, optical routing, and placement and routing considering warpage and thermal effects. Timing: New chip-level and cross-chip timing analysis techniques are desired. We address timing propagation under current source delay model (CSM), timing analysis and optimization for optical-electrical routing, multi-corner multi-mode analysis for HI, hierarchical MCMM analysis. Testing: The scope covers functional-like test generation, System-in-Package (SiP) online testing, photonic integrated circuits (PIC) testing and design-for-test (DfT), etc. Integration: We shall address chip, package, and board co-design considering multi-domain physics, including physical, electrical, thermal, mechanical, and optical effects and optimization.

Software-based self-test (SBST) is a promising solution to online self-testing of processor cores. SBST can comple-ment scan-chain-based approaches without additional hardware to improve self-test fault coverage. One of the challenges to SBST is the size of memory required to store the fault-free test responses. To reduce the memory overhead, this paper proposes a response compaction algorithm. In addition to significantly reducing the test response footprint, the algorithm is designed to incur low aliasing probability and be software friendly, i.e., it can be efficiently implemented with instructions available in most processors. Validated on a MIPS32 processor, the proposed compaction algorithm reduces the test response footprint by 84% and incurs no aliasing case.

For processor cores, software-based self-test (SBST) is a promising complement to scan-based testing, especially for applications that demand high reliability. However, most prior SBST techniques only target stuck-at faults and thus fall short in detecting aging induced timing violations. In this paper, we propose an automatic test program generator for detection of transition delay faults (TDFs) in pipelined processors. The key technique is the conversion of scan-based launch-on-capture (LoC) TDF test patterns to instruction sequences, which are combined to form the self-test program. In the field, the processor under test can execute the test program on demand, in its functional mode, to detect TDFs. To facilitate the pattern-to-instruction conversion, a test program template is developed. Derived from the pipelined processor operation, the template helps systematically and efficiently set the flip-flop values specified in LoC test patterns. The proposed technique is validated on a MIPS32 processor and achieves 97.82% transition delay fault coverage.

For high-performance integrated circuits with tight timing budgets, full-scan based transition delay fault (TDF) testing is mandatory to ensure high test quality. However, the discrepancy between the scan test mode and the functional mode is problematic. For example, the elevated switching activity during scan test application may degrade circuit performance and lead to overkill. In this paper, we address this problem by generating functional-like TDF test patterns. First, a Bayesian-based circuit model is constructed; the result is an enumeration of circuit states that closely mimics the functional mode. During test generation, the model guides the backtrace and fault propagation procedures more effectively than the conventional SCOAP or COP measures because reconvergent fanout is implicitly included in the model. Experimental results on processor benchmarks, including a MIPS32 and a RISC-V processor, show that the TDF test set generated using the Bayesian-based circuit model not only is more functional-like, but also achieves higher fault coverage.

As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become a key to beat process limitation for optimizing system performance and power consumption. Among the explored technologies, the wafer-level integrated fan-out (InFO) package-on-package (PoP) has been adopted by major companies such as TSMC to achieve high-density, high-performance, low-cost packaging solutions. To achieve a high-quality 2.5D/3D heterogeneous integration system, we shall study the chip, package, and board codesign methodology with advanced packages and explore key techniques to handle the emerging challenges in physical design, timing, electrical effects, and testing.1

Many parallel test pattern generation techniques have been proposed to speed up the test pattern generation (TPG) process. Focusing on acceleration, most of these techniques sacrifice determinism and often incur test set inflation. In this paper, a parallel TPG that exploits search space parallelism to improve fault coverage, called deterministic search-space parallel ATPG (DSSP-ATPG), is proposed. Static search space partitioning and dynamic search space allocation techniques are developed to coordinate the cooperating threads so as to reduce the thread idle time and ensure determinism. Experimental results on larger benchmark circuits and an industry circuit show that DSSP-TPG improves fault coverage as the thread count is increased. Furthermore, to speed up the TPG process, a hybrid ATPG scheme that integrates the DSSP-ATPG with a deterministic fault-parallel ATPG is implemented. By adjusting the extent of fault and search-space parallelism, the user can tune the hybrid ATPG towards higher fault coverage or more CPU time reduction.

Software-based Self-test (SBST) has been recognized as a promising complement to scan-based structural Built-in Self-test (BIST), especially for in-field self-test applications. In response to the ever-increasing complexities of the modern CPU designs, machine learning algorithms have been proposed to extract processor behavior from simulation data and help constrain ATPG to generate functionally-compatible patterns. However, these simulation-based approaches in general suffer sample inefficiency, i.e., only a small portion of the simulation traces are relevant to fault detection. Inspired by the recent advances in reinforcement learning (RL), we propose an RL-based test program generation technique for transition delay fault (TDF) detection. During the training process, knowledge learned from the simulation data is employed to tune the simulation policy; this close-loop approach significantly improves data efficiency, compared to previous open-loop approaches. Furthermore, RL is capable of dealing with delayed responses, which is common when executing processor instructions. Using the trained RL model, instruction sequences that bring the processor to the fault-sensitizing states, i.e., TDF test patterns, can be generated. The proposed test program generation technique is applied to a MIPS32 processor. For TDF, the fault coverage is 94.94%, which is just 2.57% less than the full-scan based approach.

Reconvergence has been recognized as the main reason for ATPG backtrack. It induces not only more, but also prolonged backtracks and causes more severe performance degradation than expected. In this paper, we propose a reconvergence-aware testability measure to better guide the ATPG justification process. Experiment results show that the proposed method significantly decreases the ATPG runtime, especially for circuits with deep logic level, by up to 76%.

FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and round-trip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.

FPGA-based digital IC testers have been commercialized and shown to be a promising solution for low to mid-end applications. For FPGA-based test equipment to be a practical solution, it is crucial to increase the number of channels that one single FPGA can accommodate. The objective of this work is to develop a data/timing formatter architecture that consumes less FPGA resources so as to accommodate 16 formatter channels in one Xilinx Spartan 6 FPGA. To reach this goal, the proposed formatter utilizes the more compact time/format set tables to store the pre-processed control signals and delay codes required for symbol generation. To match the time/format set table based symbol generation, a new EG (edge generator) pool structure is developed; it also lowers FPGA resource usage without sacrificing the timing accuracy. Furthermore, the EG is redesigned to reduce the controller timing complexity. The proposed 16-channel formatter has been implemented on a Xilinx Spartan 6 FPGA. Compared to the previously reported 5-channel formatter, it delivers the same performance (200 ps edge placement resolution and 100 MSPS symbol rate) without significant increase in FPGA resource usage.

With modern FPGAs' reconfiguration flexibility and abundant resources, FPGA-based test equipment has become a promising solution for low to mid-end test and measurement applications. However, FPGA structure and specifications limit the choice of tester architecture and achievable performance. In this paper, we design and implement an FPGA-based multi-channel data/timing formatter, a key component in automatic test equipment. The proposed formatter (1) adopts the EG (edge generator) pool concept to improve hardware utilization, (2) employs accuracy-driven EG scheduling to improve edge placement accuracy, (3) embeds a delay monitor for temperature compensation, and (4) allows inter-channel skew adjustment. A prototype five-channel formatter is implemented on Xilinx Spartan-6 FPGA. The per channel symbol rate is 100 Msps and the edge placement resolution is 200 ps.

The excessive circuit switching activity during scan-based at-speed testing has been known to cause yield loss because it degrades the circuit performance and can cause a good device to fail the test. In this paper, we propose an IR-drop aware test pattern generator to produce high-quality at-speed test patterns. The idea is to manage the switching activity distribution of the generated test patterns so that the resulting IR-drop profiles match the user-specified ones. To improve the efficiency of the IR-drop matching process, the maximum-implication random-fill (MIR-fill) based IR-drop matching technique is developed. Simulation results show that the proposed test pattern generator achieves 20 times speedup compared to the previous work and also delivers significant IR-drop cost reduction.

Parallelism is one promising solution to accelerating the test pattern generation (TPG) process, several recent works also show that parallel TPG can reduce the test pattern count. However, today's parallel TPG's are mostly non-deterministic, i.e., the generated test set is timing and resource dependent, this complicates the debug process and may degrade the user experience. In this paper, we propose a multi-threading parallel test pattern generator that is both deterministic and incurs zero test inflation. Called SDC-TPG, the proposed parallel TPG relies on synchronized dynamic compaction (SDC) to generate the same test pattern set as the conventional serial TPG with dynamic compaction regardless of the thread timing and the thread count. Furthermore, an early primary fault TPG strategy is proposed to reduce the thread idle times and improve the speedup. Simulation results show that SDC-TPG achieves an average speedup of six with eight threads.

The programmable delay line is one of the key components in automatic test equipment. Recently, implementation of programmable delay lines on FPGAs has drawn growing attention due to the flexibility and reconfiguration capability that FPGAs provide. In this work, we propose the subset sum delay line (SSDL) architecture for FPGA-based delay lines. The SSDL architecture takes advantage of the inevitable FPGA process variations, structure irregularities and routing uncertainties to realize high-quality FPGA-based delay lines. Furthermore, compared to previous FPGA-based delay lines, the SSDL architecture is FPGA independent, this substantially enhances its portability across different FPGA generations and suppliers. An SSDL is realized on Alter a Cyclone II FPGA. Measurement results show that it achieves 76 ps resolution and has a dynamic range of 32 ns.

Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this paper. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC schemes, we try to reconstruct the memory cells of code words such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.

This paper presents a self-testing technique for split-capacitor-array SAR ADC. In the proposed mutual characterization methodology, the capacitor array is reconfigured so that one sub-array assists the bit weight extraction of the other. Taking advantage of the split-capacitor-array architecture, mutual characterization incurs much less area overhead than previous works. From obtained bit weights, the capacitor mismatch induced nonlinearity can be derived and further calibrated via external digital calibration. Simulation results show that the proposed technique achieves high DNL/INL estimation accuracy and substantially improves the SAR ADC linearity.

Testing flat panel display source driver ICs is a costly process; the root cause is the internal DAC array which is functionally tested. This paper proposes an IDDQ-based design-for-test (DFT) technique to detect the open and short faults inside the DAC array. Compared to previous methods, the proposed DFT technique substantially improves the IDDQ testability and reduces the number of required analog measurements. Spice simulation results are presented to validate the effectiveness of the proposed technique in detecting open and short defects.

Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed; it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.

Single isolated fault (SIF) stands for about 60%-70% of the total number of defects and is rather redundancy hungry since a spare row or a column is required for repairing each SIF. Therefore, manufacturing yield will decrease if we do not allocate sufficient spare resources. In this paper, instead of the traditional fault replacement techniques, synergistic techniques that integrate both fault replacement and fault masking techniques are proposed. With our approaches, SIFs are masked instead of the traditional replacement for repairing. For other minor fault types (e.g., faulty rows and faulty columns), the fault replacement technique is used as usual. According to simulation results, repair rates can be improved significantly. The proposed techniques can be integrated with the conventional built-in self-repair with nearly negligible hardware overhead.

This paper presents an error tolerance scheme for 3-D CMOS imagers that are constructed by stacking a pixel array of imager sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using microbumps$(\mu{\rm bumps})$and through silicon vias (TSVs). To deliver high-quality images in the presence of single or multiple$\mu{\rm bump}$, ADC, or TSV failures, we propose to interleave the connections from pixels to ADCs and recover the corrupted data in the ISPs. Key design parameters, such as the interleaving stride and the grouping ratio are determined by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3-D imager from 44% to 97%.

In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived from the recorded output sequences. Numerical simulations are performed to validate the proposed technique.

Shift and capture power management has become indispensable for modern complex low-power designs. Excessive shift power increases test application time and may jeopardize the shift operation correctness, excessive capture power during at-speed scan testing may lead to yield loss. This paper proposes a scan cell design which isolates scan cells output transitions in both shift and capture modes. Experimental results on larger ISCAS'89, ITC'99, and IWLS'05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.

Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification also supports comparator offset compensation to improve calibration quality. Simulation results show that the proposed technique effectively improves the SAR ADC linearity in the presence of capacitor mismatch and comparator offset.

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.

This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.

This paper presents a low-cost pre- and post-bond self-testing and calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The basic idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of the internal digital-to-analog converter (DAC) capacitor array. During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. This substantially reduces the required design-for-test (DfT) circuitry complexity and test time. Then, during the post-bond stage, more thorough characterization on the ADC array is performed, we utilize digital resources from the image signal processor (ISP) die to analyze the measurement results, compute the calibration parameters, and perform the digital calibration. Simulation results are presented to validate the proposed techniques.

Capture power management has become a necessity to avoid at-speed scan testing yield loss, especially for modern complex and low power designs. This paper proposes a test pattern generation methodology that utilizes the available clock-gating mechanism, a popular low power design technique, to reduce the launch cycle weighted switching activity (WSA) for at-speed scan testing. Compared to previous techniques that consider clock-gating, a significant launch cycle WSA reduction is achieved without severe test pattern inflation.

This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multi-million-gate scan designs. In case the scan design contains multiple synchronous clock domains, each group of synchronous clock domains is treated as a clock group and tested using a launch aligned or a capture aligned LOC scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.1X to 2.1X, while the ATPG runtime was increased by 10% to 50%, when compared to the one-hot clocking scheme alone.

Loopback testing is a powerful technique for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) pair embedded in a mixed-signal system-on-chip (SoC). While attractive, its performance is generally limited by the achievable test resolution and the potential fault masking problem. In this work, a loopback linearity testing technique for an ADC/DAC pair is presented; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the required test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.

For two-pattern at-speed scan testing, the excessive power supply noise at the launch cycle may cause the circuit under test to malfunction, leading to yield loss. This paper proposes a new weight assignment scheme for logic switching activity; it enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model. By including the power grid network structure information, the proposed weight assignment better reflects the regional IR-drop impact of each switching event. For ATPG, such comprehensive information is crucial in determining whether a switching event burdens the IR-drop effect. Simulation results show that, compared with previous weight assignment schemes, the estimated regional IR-drop profiles better correlate with those generated by commercial tools.

This work proposes a power supply noise reduction technique for at-speed testing in the broadcast-based test compression environment. The core technology is the X-slice creation technique, it comprises the scan-chain skew-insertion hardware and the skew configuration generation algorithm. With the created X-slices, the efficiency of X-slice filling to lower the launch cycle switching activity is improved. Effectiveness of the proposed technique is validated with ISCAS89 and ITC99 benchmark circuits.

A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using micro-bumps (μbumps) and through-silicon vias (TSVs) is promising for high throughput applications. However, due to the direct mapping from pixels to ISPs, the overall yield relies heavily on the correctness of the μbumps, ADCs and TSVs -- a single defect leads to the information loss of a tile of pixels. This paper presents an error tolerance scheme for the 3D CMOS imager that can still deliver high quality images in the presence of μbump, ADC, and/or TSV failures. The error tolerance is achieved by properly interleaving the connections from pixels to ADCs so that the corrupted data, if any, can be recovered in the ISPs. A key design parameter, the interleaving stride, is decided by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3D imager from 46% to 99%.

This paper presents a robust, low-cost ADC code hit counting technique to record the number of times each ADC output code word appears with respect to the ramp input. Using a smart center code tracking engine, the proposed code hit counter performs robustly against the code transition noise, missing code segments, and non-monotonicity; furthermore, the required hardware and test time is at the same level as the known best results. The robustness together with the low overhead makes the proposed code hit counter suitable for (on-line) ADC self-testing and self-calibration applications.

Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.

This paper presents a loopback methodology for static linearity testing of an ADC/DAC pair; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the needed test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.

This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.

Integrator leakage is a dominant factor in the SNR (signal-to-noise ratio) loss of ΔΣ modulators. In this paper, we propose a Design-for-Test (DfT) technique to diagnose the integrator leakage of the single-bit first-order ΔΣ modulator. The proposed technique is a low-cost solution; it only adds two multiplexers to the modulator, utilizes a single DC voltage as the test stimulus, and estimates the integrator leakage by analyzing the digitized bit stream. Furthermore, the technique can be easily extended to higher order ΔΣ modulators. Simulation results show that accurate estimations of the integrator leakage can be achieved even at the presence of noise.

This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator offset. Together with existing SC testing techniques, the leakage characterization technique helps better characterize SC circuits; its application to several popular SC circuits is demonstrated.

Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. AlthoughX-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This paper solves this problem by proposing a novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-powerX-filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by benchmark circuits, as well as an industry design in the embedded deterministic test environment.

This paper presents a low-cost wafer-level test methodology for the source driver ICs of liquid crystal displays; the idea is to realize the test circuitry on the wafer scribe line. The proposed technique not only substantially reduces the required ATE I/O channels but also eliminates the need of high-speed digitization units on the ATE. Furthermore, because the test circuitry is realized on the scribe line, no modification is made to the circuit under test, i.e., the proposed methodology does not incur any area or performance overhead.

This paper presents PHS-Fill, an ATPG technique that reduces(1) power supply noise for scan-based at-speed testing, and(2) test data volume in a Huffman coding based test compression environment. PHS-Fill first identifies the preferred Huffman symbols; these symbols correspond to the test pattern templates that improve test compression and reduces power supply noise at the same time. ATPG then biases its primary input assignments so that the test pattern blocks match the preferred symbols whenever possible. Simulation results on ISCAS89 and ITC99 benchmark circuits show that PHS-Fill is a promising solution.

Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This work is the first to solve this problem by proposing a novel integrated ATPG scheme that efficiently and effectively performs compressible X-filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by large benchmark circuits as well as an industry design in the embedded deterministic test (EDT) environment.

For modern display systems, thorough testing of the TFT array is a critical element in yield management. However, for system-on-panel displays which integrate drivers, timing units, and controllers on the same substrate (usually glass) as the TFT array, access to the array data and scan lines is complicated. To reduce the tester complexity, we propose a low area overhead and offset compensated charge sensing capable source driver design which facilitates built-in TFT array charge sensing. To reduce the number of test access ports, a serial voltage readout scheme is proposed. Simulation results using LTPS technology are shown to validate the proposed technique.

Power management is posing serious challenges for scan-based testing. In this paper, we propose a low power test pattern generation technique which minimizes the peak power consumption associated with the scan and capture operations. Given a set of fully specified test patterns, the proposed technique iteratively replaces the high power consumption patterns with low power ones generated by a PODEM-based low power ATPG. The proposed technique has been validated using ISCAS89 benchmark circuits. Compared to a commercial ATPG using high merge ratio and random-fill options, the proposed technique reduces the peak shift and capture power by 27.3% and 19.6%, respectively, and the average power by 49.9%.

For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation during the physical design stage. In this paper, a scan chain ordering technique for test power reduction under user-specified routability constraints is presented. The proposed technique allows the user to explicitly set the routing constraints and the achievable power reduction is rather insensitive to the routing constraints. The proposed method is applied to six industrial designs. The achievable power reduction is in the range of 37-48% without violating any user-specified routing constraint.

In this paper, a random jitter (RJ) extraction technique in the presence of sinusoidal jitter (SJ) is proposed for on-chip jitter tolerance testing applications. First, the period-tracking technique (Kuo and Huang, 2006) is utilized to derive the SJ frequency and amplitude information. Then, using the same design-for-test (DfT) circuitry, samples from the total jitter cumulative distribution function (CDF) are taken. From the SJ information and CDF samples, a binary search method is utilized to obtain the RJ sigma value. The features of the proposed technique include low delay line resolution requirement and high process variation tolerance. Simulation results are performed and shown to validate the proposed technique

In this paper, a low-cost and process-insensitive random jitter testing algorithm is proposed for on-chip design-fortest applications. The algorithm incurs low hardware cost as it utilizes a low tap-count delay line to extract the RMS jitter information. Furthermore, the proposed algorithm can tolerate reasonable delay line deviations. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line deviations.

In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two different delay values and the probabilities it leads the two delayed versions are measured. The RMS period jitter value can then be derived from the probabilities and the delay difference. Both behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and a prototype chip has been designed for further validation.

In this paper, we present a technique to measure the RMS period jitter of the signal under test. In the proposed approach, the lead/lag relationships between the signal under test and two delayed versions of itself are compared. The collected information corresponds to two points along the jitter's cumulative distribution function (CDF) curve from which the RMS period jitter value can be derived. Currently, SPICE simulation results show less than 5% error for RMS jitter values ranging from 40 to 60 ps.

Because of their relative robustness to process variation, /spl Sigma/-/spl Delta/ modulation techniques are particularly suitable for VLSI implementations. In this paper, we propose to employ the 1-bit /spl Sigma/-/spl Delta/ modulation ADC (analog-to-digital converter) as the on-chip analog response extractor for analog/mixed-signal BIST (built-in self-test) applications. To validate the idea, a prototype chip with the proposed BIST circuitry has been designed and fabricated. Performance of the BIST circuitry is validated (up to 87 dB dynamic range), and measurement results of the circuit under test (CUT), a 2nd-order low-pass filter, are presented.

In this paper, we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specifications, e.g., the rise/fall time of modern high-speed communication transceivers. To reduce hardware overhead, the proposed BIST technique uses the coherent under-sampling principle, and measures implicitly the time interval in a two-pass manner. Simulation results are shown to validate the proposed technique.

In this work, we present the analysis of a built-in self-test (BIST) scheme for mixed-signal circuits that is intended to provide on-chip stimulus generation and response analysis.Based on the sigma-delta modulation principle, the proposed scheme can produce high-quality stimuli and obtain accurate measurements without the need of precise analog circuitry.Numerical simulations are conducted to validate our idea and the results show that the scheme is a promising BIST approach for mixed-signal circuits.

In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.

Delta-sigma modulation has become popular in modern analog-to-digital modulator design due to its relatively high immunity from process variations. We propose efficient characterization techniques to obtain the key performance parameters of the 1-bit first-order delta-sigma modulator which is intended to be used as an on-chip analog signal digitizer for BIST applications. Numerical simulations have been performed to validate the techniques and the results indicate that accurate estimation of the parameters can be obtained at the presence of noise.

In this paper, we characterize and evaluate the effectiveness of a pseudo-random-based implicit functional testing technique for analog and mixed-signal circuits. The analog test problem is transformed into the digital domain by embedding the device-under-test (DUT) between a digital-to-analog-converter and an analog-to-digital converter. The pseudo-random testing technique uses band-limited digital white noise (pseudo-random-patterns) as input stimulus. The signature is constructed by computing the cross-correlation between the digitized output response and the pseudo-random input sequence. We have implemented a DSP-based hardware testbed to evaluate the effectiveness of the pseudo-random testing technique. Our results show that we can achieve close to 100% yield and fault coverages by carefully selecting only two cross-correlation samples. Noise level and total harmonic distortion below 0.1% and 0.5%, respectively, do not affect the classification accuracy.

In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing fault simulation only locally for the fault block. Simulation results on an industrial design show a speedup factor of 7.2 with 98% correct classification of detected and undetected faults as compared with full-chip DC fault simulation.

We present key portions of a method for automatic analog fault diagnosis for unpowered circuit boards. Our work consists of two major parts: (1) test point selection and (2) stimuli selection for diagnostic test generation. For test point selection, we propose an efficient graph-based algorithm achieving a desired level of diagnosibility. The stimuli selection algorithm uses a cost function derived from the sensitivity matrix to select test stimuli and thus avoids expensive circuit simulation. Experimental results of several industrial circuits show that our method is time efficient and promising in selecting high-quality stimuli.