The increasing demand for high-performance query processing on large in-memory datasets has driven the adoption of GPU-based B+-trees for handling high-concurrency query (HCQ) workloads. Existing approaches, by randomly assigning queries to GPU threads, suffer from inefficiencies related to memory access patterns, cache utilization, and thread divergence. This paper introduces a novel query grouping strategy that assigns queries with similar search keys to the same CUDA block, thereby improving query throughput. We formalize the optimal key assignment (OKA) problem as a variation of the K-means problem, establishing its theoretical foundations and proposing an efficient algorithm with proven optimality. We implement this algorithm using highly optimized CUDA code and extend our approach to support range queries, a common but understudied workload in GPU-based HCQ systems. Experimental evaluations demonstrate that our query grouping strategy significantly outperforms prior work, achieving up to 10.6X lower latency and 32.2X higher throughput, while also improving GPU resource utilization (e.g., cache hit rate and memory throughput).

The rapid growth of Internet of Things (IoT) devices has heightened hardware security concerns, particularly with the emergence of hardware Trojans (HTs) as malicious components in integrated circuits. These HTs pose significant threats to information privacy and system performance. The early detection methods rely on golden references and domain knowledge, limiting their implementation in large-scale integrated circuits. Traditional machine learning-based HT detections can effectively identify infected circuits without golden chips. However, locating and evaluating the specific behavior of HTs in vast and complex circuits is challenging. To address these challenges, this paper presents an HT Object Detection (HTOD) problem, which involves two primary tasks: identifying the boundaries and sizes of HTs within circuits and distinguishing between different HT behaviors. We have developed a two-stage HT object detection framework based on a bidirectional jumping knowledge network called HTOD-BGNN to solve the HTOD problem, which enables progressive refinement of localized regions. It incorporates enhanced base-type features to ensure scalability and information retention during modeling. Additionally, the implementation of sample augmentation alleviates the challenges of sample imbalance and scarcity. The proposed method enables more intelligent circuit detection, achieving 100% and 87.5% detection rates for Trojan triggering and payload behaviors, respectively. It demonstrates superior localization performance and effective generalization to unseen circuit scenarios via its region refinement mechanism, achieving F1-scores of 54.01% on TrustHub and 90.04% on TRIT datasets.

In order to better utilize the achievements of various countries and lower costs, the integrated circuit (IC) design and manufacturing process is based on a global supply chain model, highly relying on untrusted third parties, such as intellectual property (IP) cores, electronic design automation (EDA) tools, and employees. This globalized model creates lots of opportunities for the prosperity of hardware Trojans (HTs). However, existing countermeasures were all accomplished under some assumptions, such as finding HTs in a complete netlist. In practical industry scenarios, netlists may be obtained through reverse engineering, which has inherent limitations, including imaging resolution and inaccurate recognition of interconnections, making it almost impossible to obtain a complete netlist to detect whether HTs exist. Evidently, studying how to find HTs from incomplete netlists should be a reasonable, notable, critical and practical issue for the IC security research community. Addressing this problem entails substantial challenges. This paper is the first to propose the problem of detecting HTs with incomplete netlists, and also presents an effective approach named HTINS, which infers and completes incomplete circuit structures and utilizes the completed information for HTs detection. The method leverages GraphVAE to reconstruct incomplete netlist components and performs circuit feasibility validation on the reconstructed components. Local features are then extracted from the completed circuits and classified via a graph neural network. In the experiments, netlist components are randomly removed to set netlists with 1%, 5%, and 10% missing ratios, and the performance of HT detection on the completed netlists is evaluated under these conditions. Experimental results demonstrate that the proposed method can effectively reconstruct incomplete netlists and significantly improve HT detection performance.

The globalization of integrated circuit design and manufacturing has brought about extremely dangerous hardware Trojans (HT). One critical HT detection method is reverse engineering, which is used to restore design files to detect HTs. However, whether current reverse engineering can accurately reconstruct detailed design information, including partial netlists, remains uncertain. Meanwhile, numerous current HT detection methods based on machine learning are generally based on the ideal assumption that "the netlist is complete and available". This makes such models significantly reduce the detection accuracy and stability when facing practical applications due to the interference of part of the netlist. Therefore, exploring HT detection of partial netlists is cutting-edge. To address the above issues, we propose RE-PNRL, a Reinforcement Learning-based framework for reconstructing Partial Netlists using node-level transition probabilities. We also introduce a clustering-based hardware Trojan detection method that uses the complete netlist to identify potential threats. Experiments show that our method achieves average TPR and TNR of 66.39% and 73.72%, respectively, while the clustering-based detection achieves 96.80% TPR and 94.80% TNR, outperforming state-of-the-art approaches. Further validation on Trojan benchmarks confirms its effectiveness under different levels of netlist missingness.

Due to the complexity of integrated circuit design and manufacturing process, an increasing number of third parties are outsourcing their untrusted Intellectual Property (IP) cores to pursue greater economic benefits, which may embed numerous security issues. The covert nature of hardware Trojans (HTs) poses a significant threat to cyberspace, and they may lead to catastrophic consequences for the national economy and personal privacy. To deal with HTs well, it is not enough to just detect whether they are included, like the existing studies. Same as malware, identifying the attack intentions of HTs, that is, analyzing the functions they implement, is of great scientific significance for the prevention and control of HTs. Based on the fined detection, for the first time, this paper proposes a two-stage Graph Neural Network model for HTs’ multifunctional classification, GNN4HT. In the first stage, GNN4HT localizes HTs, achieving a notable True Positive Rate (TPR) of 94.28 the Trust-Hub dataset and maintaining high performance on the TRTC-IC dataset. GNN4HT further transforms the localization results into HT Information Graphs (HTIGs), representing the functional interaction graphs of HTs. In the second stage, the dataset is augmented through logical equivalence for training and HT functionalities are classified based on the extracted HTIG from the first stage. For the multifunctional classification of HTs, the correct classification rate reached as high as 80.95% at gate-level and 62.96% at RTL. This paper marks a breakthrough in HT detection, and it is the first to address the multifunctional classification issue, holding significant practical importance and application prospects.

Active learning (AL) tries to maximize the model’s performance when the labeled data set is limited, and the annotation cost is high. Although it can be efficiently implemented in deep neural networks (DNNs), it is questionable whether the model can maintain the ability to generalize well when there are significant distributional deviations between the labeled and unlabeled data sets. In this article, we consider introducing adversarial training and adversarial samples into AL to mitigate the problem of degraded generalization performance due to different data distributions. In particular, our proposed adversarial training AL (ATAL) has two advantages, one is that adversarial training by different networks enables the network to have better prediction performance and robustness with limited labeled samples. The other is that the adversarial samples generated by the adversarial training can effectively expand the labeled data set so that the designed query function can efficiently select the most informative unlabeled samples based on the expanded labeled data set. Extensive experiments have been performed to verify the feasibility and efficiency of our proposed method, i.e., CIFAR-10 demonstrates the effectiveness of our method—new state-of-the-art robustness and accuracy are achieved.

With the future 6G era, spiking neural networks (SNNs) can be powerful processing tools in various areas due to their strong artificial intelligence (AI) processing capabilities, such as biometric recognition, AI robotics, autonomous drive, and healthcare. However, within Cyber Physical System (CPS), SNNs are surprisingly vulnerable to adversarial examples generated by benign samples with human-imperceptible noise, this will lead to serious consequences such as face recognition anomalies, autonomous drive-out of control, and wrong medical diagnosis. Only by fully understanding the principles of adversarial attacks with adversarial samples can we defend against them. Nowadays, most existing adversarial attacks result in a severe accuracy degradation to trained SNNs. Still, the critical issue is that they only generate adversarial samples by randomly adding, deleting, and flipping spike trains, making them easy to identify by filters, even by human eyes. Besides, the attack performance and speed also can be improved further. Hence, Spike Probabilistic Attack (SPA) is presented in this paper and aims to generate adversarial samples with more minor perturbations, greater model accuracy degradation, and faster iteration. SPA uses Poisson coding to generate spikes as probabilities, directly converting input data into spikes for faster speed and generating uniformly distributed perturbation for better attack performance. Moreover, an objective function is constructed for minor perturbations and keeping attack success rate, which speeds up the convergence by adjusting parameters. Both white-box and black-box settings are conducted to evaluate the merits of SPA. Experimental results show the model's accuracy under white-box attack decreases by 9.2S%~31.1S% better than others, and average success rates are 74.87% under the black-box setting. The experimental results indicate that SPA has better attack performance than other existing attacks in the white-box and better transferability performance in the black-box setting,

As an emerging lab-on-a-chip technology platform, digital microfluidic biochips (DMFBs) have been widely used for executing various laboratory procedures in biochemistry and biomedicine such as gene sequencing and near-patient diagnosis, with the advantages of low reagent consumption, high precision, and miniaturization and integration. With the ongoing rapid deployment of DMFBs, however, these devices are now facing serious and complicated security challenges that not only damage their functional integrity but also affect their system reliability. In this article, we present a systematic review of DMFB security, focusing on both the state-of-the-art attack and defense techniques. First, the overall security situation, the working principle, and the corresponding fabrication technology of DMFBs are introduced. Afterwards, existing attack approaches are divided into several categories and discussed in detail, including denial of service, intellectual property piracy, bioassay tampering, layout modification, actuation sequence tampering, concentration altering, parameter modification, reading forgery, and information leakage. To prevent biochips from being damaged by these attack behaviors, a number of defense measures have been proposed in recent years. Accordingly, we further classify these techniques into three categories according to their respective defense purposes, including confidentiality protection, integrity protection, and availability protection. These measures, to varying degrees, can provide effective protection for DMFBs. Finally, key trends and directions for future research that are related to the security of DMFBs are discussed from several aspects, e.g., manufacturing materials, biochip structure, and usage environment, thus providing new ideas for future biochip protection.

As the next generation of digital microfluidic biochips (DMFBs) platform, Micro-electrode-dot-array (MEDA) has sea-of-micro-electrodes that support fine-grained control of the droplet and constant real-time monitoring of droplet paths. As MEDA biochips are expected to be had a booming market in the near future, their security, especially the protection of intellectual property (IP), has become the focus of the academic community. In this paper, we first propose a logic encryption-based IP protection scheme for MEDA biochips, called MEDASec, which is without modifying the structure. Our scheme aims to hide the droplet mix-split operation in bioassay, making the IP akin to a black-box in the manufacturing process. Besides, increasing computing power has facilitated the threat of brute force attacks on the secret key. In response to the brute force attack, we propose security metrics for the first time, called RRA, to evaluate the ratio of reagents that result from biochemical reactions. Experimental results on multiple bioassays demonstrate the effectiveness of the proposed logical encryption strategy against the brute force attack.

Industry 4.0 intends to realize mass individualization production driven by customers’ demands, thus generating several advanced manufacturing modes. However, the existing modes have disadvantages such as low customer participation, low response for modifications in real-time, and low utilization of distributed idle productivity resources. The above deficiencies would not cater to the idea of Industry 4.0 well, making the cost of individualization products too high or the degree of individualization too low. In this paper, a customer highly involved dynamic demand-driven smart manufacturing mode and a mathematical model are presented for mass individualization production. Under this mode, customers can be prosumers, participating in the whole production process and proposing modifications. Meanwhile, multiple distributed idle productivity resources are employed with dynamic demand-driven manufacturing. In consequence of the mathematical model and algorithms, the multiple task allocation among multiple factories problem is solved, maximizing the total profit of available factories with high efficiency and low resource waste. Experiments and comparisons are made about the feasibility and efficiency of the algorithms.

Recent advances in resistive synaptic devices have enabled the emergence of brain-inspired smart chips. These chips can execute complex cognitive tasks in digital signal processing precisely and efficiently using an efficient neuromorphic system. The neuromorphic synapses used in such chips, however, are very sensitive to the external environment, thereby weakening their resistance to malicious modifications such as hardware Trojans and backdoors. Accordingly, in this paper, we propose HTcatcher, a security verification technique for hardware threat detection in neuromorphic computing systems, incorporating finite state machine and feature verification simultaneously, which has never been considered in prior work. Furthermore, we propose a pseudo-random matrix verifying technique for memory optimization, which can reduce the memory overhead of the multi-dimensional features in the system significantly. Experimental results confirm that the proposed method can identify the malicious modifications in the system accurately, while reducing the memory usage by 25%-50%.