Traditional CMOS-based von-Neumann computer architecture faces the issue of memory wall that the limitation of bus-bandwidth and the speed mismatch between processor and memory restrict the efficiency of data processing along with an irreducible energy consumption conducted by data movement, especially in some data-intensive applications. Recently, some novel in-memory computing (IMC) paradigms developed by utilizing the characteristics of different non-volatile memories provide promising ways to overcome the bottleneck of memory wall. Here, we propose a new IMC unit based on a memory array with the core element of magnetoelectric spin-orbit logic (MESO) device (AIMCU-MESO), in which the characteristics of the MESO device are exploited to achieve several in-memory logic operations with the functions of NAND, NOR, and XOR in the MESO-based memory array. With the aid of some transistor-based switches, these logic operations can be achieved between any two MESOs in the array. Furthermore, the computing process of a 1-bit full adder (FA) is achieved in AIMCU-MESO by the in-memory logic manner to demonstrate the ability of logic cascading. The result of SPICE simulation for achieving the 1-bit FA using MESO devices is demonstrated, and the performances are compared with other designs of spintronics-based devices. Compared to multilevel voltage-controlled spin-orbit torque–based magnetic memory, the proposed design demonstrates 71.4% and 49.2% reductions in terms of storage delay and logic delay, respectively.

The RRAM-based accelerators have become very popular candidates for neural network acceleration due to they perform matrix-vector multiplication in-memory with high storage density and low latency. Many related works have used fixed-precision quantization to achieve the model compression and enhance the tolerance of process variation, but these methods still suffer a large accuracy degradation and poor robustness to nonideal effects. In this work, we propose a crossbar-aware mixed-precision quantization scheme, which enables to search for the optimal precision of each part of the network as a way to improve the accuracy and robustness to noise. First, we introduce a group quantization strategy that can flexibly adjust the group size dynamically according to the crossbar size. Then, we propose a detailed mixed-precision search flow to search for the optimal precision set of the network. Finally, we give a noise injection adaption training method to enhance the tolerance of noise. Experimental results show that our proposed method can improve inference accuracy by at least 2.04% compared to the fixed-precision quantization under the same resource cost. The searched architecture with the highest accuracy most accurate (MA) could achieve an accuracy of 92.39% and a resource saving of 93.30% compared to the full precision model. The searched architecture with the biggest resource savings most efficient (ME) could achieve an accuracy of 91.11% and a resource saving of 95.57% compared to the full precision model. And, the average precision of the ME mixed-precision architecture is only 1.4 bits. Besides, the results show the mixed-precision network with noise adaption training is more robust to noise than the fixed-precision network with noise adaption training.

In-memory computing based on memristor has attracted significant interest in order to break the von Neumann computer architecture's data-transfer bottleneck and develop high-efficient computing systems. Memristor- based logic gate is one of the potential ways to achieve these goals. Recently, there are many methods which have been presented to achieve Boolean functions, such as material implication (IMP). IMP logic gate consists of two parallel memristors, which can achieve IMP logic operation by applying appropriate voltages to memristors. With the help of IMP logic gate's structure, we could achieve many other Boolean functions by applying different voltages. We deduce the formulas which represent the relationships between applied voltages and memristors' resistances based on IMP logic gate's structure for achieving other Boolean functions. And according to these formulas, we design the schemes of applying voltages and demonstrate these designs with SPICE simulation. In addition to this, the new structure which consists of two antiparallel memristors is taken into consideration. Similarly, based on it, we deduce the formulas and design the schemes of applying voltages and demonstrate these with SPICE simulation.

Memristor-based stateful logic demonstrates a method of in-memory computing, which is a promising way to overcome the data-transfer bottleneck in the current von Neumann computer architecture. However, due to the instability, the memristor device exhibits an inherent stochastic switching behavior especially when the applied voltage is in the switching range of unsafe writing. In such case, the delicate design of stateful memristor gates could suffer the reliability problem. Here, such unsafe writing impacts on the memristor-based logic operation is systematically analyzed. Through establishing the Markov chain model of unsafe writing effects, we deduce the mathematical relationship between the material implication (IMP) logic gate reliability and switching probability. It reveals that unsafe writing with enough operation time would make the IMP logic converge to always True logic. The best operation time for the unsafe write is then proposed to improve the probability of right logic function and avoid the undesired logic result, which is demonstrated with simulation.

With the rapid development of VLSI industry, the research of intelligent applications moves towards IoT edge computing. While the power consumption and area cost of deep neural networks usually exceed the hardware limitation of edge devices. In this paper, we propose a low-power neural network architecture to address such problem. We simplify the current popular convolutional neural networks structure, and utilize the memristor crossbar to store weights to execute convolution operation in parallel, and we present the spiking convolutional neural networks. At the same time, we proposed a performance metrics V to help provide design guidelines for choosing the parameters of the network.

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current (IW), ON/OFF-state resistance (RON/ROFF), and I-V nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high RON) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With RON= 500 kΩ (IW= 6 μA) and nonlinearity ratio = 10, 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with ~2-pJ/bit energy consumption.