Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Yen-Pin Chen

dblp:47/4101 · DBLP profile ↗
← Back
4ranked-venue papers
2as first author
1since 2021 · last 2022
0000-0002-2473-0847ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
engineering change order
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
logic synthesis
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
physical design
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › logic synthesis
technology mapping
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › logic synthesis › technology mapping
technology remapping
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › physical design
timing optimization
0.112010
ECO Timing Optimization Using Spare Cells and Technology Remapping · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010

Methods — techniques the papers use, named apart from their topics

gate sizing · 0.1dynamic programming · 0.1buffer insertion · 0.1
YearPublicationVenuePosition
2022 Combining attention with spectrum to handle missing values on time series data without imputation
abstract
In the development of predictive models, the problem of missing data is a critical issue that traditionally requires a two-step analysis. Data scientists analyze the patterns of missing values, select variables, impute missing values on the basis of domain knowledge, and then train a model. Models typically have their input sizes hardcoded, and have limitations in handling data with high missing rates or changes in available variables. We propose an attention-based neural network combined with a novel real number representation, which requires little work on manually selecting variables, and in which missing data can be overlooked, making imputation unnecessary. In this proposed model, data analysis can be one step, omitting the first step of imputing missing values. The study included data on 32,709 intensive care unit (ICU) admissions and 60 healthcare variables from the Medical Information Mart for Intensive Care (MIMIC)-IV. The proposed algorithm yielded an area under the receiver operating characteristic curve (AUC) of 0.842 (95% CIs: 0.828–0.856) when predicting prolonged length of stay in the ICU, outperforming current approaches using imputation methods. The proposed algorithm can be applied to a range of problems in data science, as it addresses the issue of incomplete data with automatic variable selection.
Yen-Pin Chen, Chien-Hua Huang, Yuan-Hsun Lo, Yi-Ying Chen, Feipei Lai
Inf. Sci.1
2018 A novel depth estimation algorithm of chest compression for feedback of high-quality cardiopulmonary resuscitation based on a smartwatch
Tsung-Chien Lu, Te-Wei Ho, Yao-Ting Chang, Yi-Ting Lee, Yu-Siang Wang, Yen-Pin Chen, Chia-Ming Fu, Wen-Chu Chiang, Matthew Huei-Ming Ma, Cheng-Chung Fang, Feipei Lai, Anne M. Turner
J. Biomed. Informatics7
2010 ECO Timing Optimization Using Spare Cells and Technology Remapping
abstract
We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the spare-cell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.
Kuan-Hsien Ho, Yen-Pin Chen, Eric Jia-Wei Fang, Yao-Wen Chang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2007 ECO timing optimization using spare cells
abstract
We introduce in this paper a new problem of ECO timing optimization using spare-cell rewiring and present the first work for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost. For the addressed problem, we present a framework of buffer insertion and gate sizing to handle it. In this framework, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming (DCP), for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.
Yen-Pin Chen, Eric Jia-Wei Fang, Yao-Wen Chang
ICCAD1