This paper presents a novel low-complexity discrete Fourier transform spread orthogonal frequency division multiplexing (DFT-s-OFDM) scheme designed to reduce computational overhead while maintaining robust performance in wireless communication systems. The core idea is to modify the signal processing chain by merging the computations of multiple functional blocks, resulting in a significant reduction in the complexity of conventional DFT-s-OFDM implementations. A comparative analysis is conducted to evaluate the proposed scheme against traditional DFT-s-OFDM, using key metrics such as error vector magnitude (EVM) and computational complexity. Simulation results demonstrate that the proposed scheme achieves performance comparable to conventional DFT-s-OFDM in terms of EVM under various system configurations, while significantly reducing computational complexity. This makes the proposed scheme a promising candidate for next-generation wireless communication systems, particularly in uplink scenarios involving battery-powered devices.

Proposed cache compression schemes make design-time assumptions on value locality to reduce decompression latency. For example, some schemes assume that common values are spatially close whereas other schemes assume that null blocks are common. Most schemes, however, assume that value locality is best exploited by fixed-size data types (e.g., 32-bit integers). This assumption falls short when other data types, such as floating-point numbers, are common. This paper makes two contributions. First, HyComp -- a hybrid cache compression scheme -- selects the best-performing compression scheme, based on heuristics that predict data types. Data types considered are pointers, integers, floating-point numbers and the special (and trivial) case of null blocks. Second, this paper contributes with a compression method that exploits value locality in data types with predefined semantic value fields, e.g., as in the exponent and the mantissa in floating-point numbers. We show that HyComp, augmented with the proposed floating-point-number compression method, offers superior performance in comparison with prior art.

It is well known that to be able to represent continuous functions between domain representable spaces it is critical that the domain representations of the spaces we consider are dense. In this article we show how to develop a representation theory over a category of domains with morphisms partial continuous functions. The raison d'être for introducing partial continuous functions is that by passing to partial maps, we are free to consider totalities which are not dense. We show that the category of admissibly representable spaces with morphisms functions which are representable by a partial continuous function is Cartesian closed. Finally, we consider the question of effectivity.

In our quest to bring down the power consumption in low-power chip-multiprocessors, we have found that TLB and snoop accesses account for about 40% of the energy wasted by all L1 data-cache accesses. We have investigated the prospects of using virtual caches to bring down the number of TLB accesses. A key observation is that while the energy wasted in the TLBs are cut, the energy associated with snoop accesses becomes higher. We then contribute with two techniques to reduce the number of snoop accesses and their energy cost. Virtual caches together with the proposed techniques are shown to reduce the energy wasted in the L1 caches and the TLBs by about 30%.

In the coming few years, three trends for mobile phones will be seen. First, new communication standards provide packet-switched high-bandwidth wireless communication globally. Second, user applications are going from simple phone administration and text messaging to advanced multimedia and entertainment applications. Finally, because of Internet access and security support, the phones have the potential to move into a financial instrument for economical transactions. The article mainly covers the two former trends, and describes key complexity issues and design challenges. The concept of future mobile phones is described; communication capabilities and some emerging user application capabilities are outlined. The article describes and discusses complexity issues and some design challenges, and also provides a summary. Overall, the focus is from the digital system architecture perspective, and does not cover challenges in the areas of radio, antenna, or analog/digital integration.

Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there is enough work processing a node that the prefetch latency can be hidden, or when the LDS is long enough and the traversal path is known a priori. This paper presents a prefetching technique called prefetch arrays which can prefetch both short LDS, as the lists found in hash tables, and trees when the traversal path is nor known a priori. We offer two implementations, one software-only and one which combines software annotations with a prefetch engine in hardware. On a pointer-intensive benchmark suite, we show that our implementations reduce the memory stall lime by 23% to 51% for the kernels with linked lists, while the other prefetching methods cause reductions that are substantially less. For binary-trees, our hardware method manages to cut nearly 60% of the memory stall time even when the traversal path is not known a priori. However, when the branching factor of the tree is too high, our technique does not improve performance. Another contribution of the paper is that we quantify pointer-chasing found in interesting applications such as OLTP, Expert Systems, DSS, and JAVA codes and discuss which prefetching techniques are relevant to use in each case.

The performance gap between processors and memory is increasing, making the cache hit-rate paramount for performance. Studies show room for improvement, especially in data caches. The cache effectiveness is dictated by software locality, hence the software behavior directs the cache performance. This paper presents a framework for studying spatial locality. It focuses on the characteristics of the spatial locality in terms of closeness in time and space, to get the amount of accessed sequential data and the potential for cache hits. By using the framework we gain knowledge for improving the cache performance. Our experiment consists of a program driven simulator and 11 important applications. We show a large performance potential in the data cache with up to 75% less miss rate, exploiting spatial locality. In order to investigate where potential bottlenecks are located we make a simple implementation of a scheme to exploit this spatial locality.

Parallel programs that modify shared data in a cache-coherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisitions at writes to shared data. This can have a significant impact on performance in a cache-coherent non-uniform memory architecture (NUMA) multiprocessor. By combining a read-request and an ownership acquisition, the write latency and network traffic can potentially be reduced. In this paper we propose a new hardware-based approach far performing this optimization by targeting load-store sequences, which we show is a super-set of migrator sharing. A load-store sequence consists of a global read request followed by a global write action to the same memory, location from the same processor without any intervening access to the same block from any other processor. We use detailed simulation with four benchmark programs including one on-line transaction processing (OLTP) workload and operating system execution to examine the effectiveness of the proposed technique. The results show that the technique is able to reduce write-related latency and network traffic more than previous hardware-based techniques, up to twice as much.

Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, TLB misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs.

On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the database server and the operating system. One contributing source is a large amount of load-store sequences in the program, resulting in many read misses as well as much global invalidation traffic. In this paper, we characterize the nature of these load-store sequences, and analyze contributing code- and data structures in the database handler, operating system, and system libraries. We explore two conceptually different approaches for detecting load-store sequences; data-centric and instruction-centric, and the goal is to load the cache block exclusively already at the load instruction so that the store instruction can perform locally. Our results were obtained using program-driven simulation of a TPC-B based workload on a four-node multiprocessor. The results show that there is a substantial amount of load-store sequences in the database handler, the operating system, and in system libraries, and about 40% of all global writes belong to such sequences. Even though the techniques were able to reduce the execution time for the application by up to 10%, the complex behavior of the database workload reduced the effectiveness of traditional optimization techniques for migratory sharing.

The design and implementation of embedded microprocessors is on the verge of change -with MCM, flip-chip and integrated DRAM/ logic technologies moving from feasible to commercially viable.Embedded DRAM memory provides a high memory bandwidth together with low latency.However, when such a system is extended with further memory, the processor is exposed to a nonuniform memory hierarchy -where some fraction of the total memory has significantly lower access latency than the remainder.In this paper, we evaluate various hardware-orientated approaches to the management of embedded memory.In addition to static page placement and conventional cache functionality, we explore novel memory management schemes that exploit temporal locality while still using the embedded DRAM as part of the physical memory space.Using execution driven simulation of real workloads, we show that this technique can deliver as much as a factor of two speedup over a conventional memory hierarchy.More importantly, we show how the embedded memory can be used to provide both data storage and a caching capability equivalent to a more complex processor device.These results imply that designers of embedded and small-scale systems can achieve significant performance wins, through the use of a combined processor/ memory device and the memory system design proposed.

The goal of this paper is to gain insight into the relative performance of communication mechanisms as bisection bandwidth and network latency vary. We compare shared memory with and without prefetching, message passing with interrupts and with polling, and bulk transfer via DMA. We present two sets of experiments involving four irregular applications on the MIT Alewife multiprocessor. First, we introduce I/O cross-traffic to vary bisection bandwidth. Second, we change processor clock speeds to vary relative network latency. We establish a framework from which to understand a range of results. On Alewife, shared memory provides good performance, even on producer-consumer applications with little data-reuse. On machines with lower bisection bandwidth and higher network latency, however, message-passing mechanisms become important. In particular, the high communication volume of shared memory threatens to become difficult to support on future machines without expensive, high-dimensional networks. Furthermore, the round-trip nature of shared memory may not be able to tolerate the latencies of future networks.

We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with memory accesses and include a hardware prefetching scheme, a migratory sharing optimization, and a competitive-update mechanism. Since each extension targets distinct components of the read and write penalties, they can be combined effectively. This paper identifies the combinations yielding the best performance gains and cost trade-offs in the context of a class of cache-coherent NUMA (Non-Uniform Memory Access) architectures. Detailed architectural simulations of a multiprocessor with single-issue, statically scheduled CPUs, using five benchmarks, show that the protocol extensions often provide additive gains when they are properly combined. For example, the combination of prefetching with the competitive-update mechanism speeds up the execution by nearly a factor of two under release consistency. The same speedup is obtained under sequential consistency by combining prefetching with the migratory sharing optimization. This paper shows that a basic write-invalidate protocol augmented by appropriate extensions can eliminate most memory access penalties without any support from the programmer or the compiler.

In a multiprocessor with a Cache-Only Memory Architecture (COMA) all available memory is used to form large cache memories called attraction memories. These large caches help to satisfy shared memory accesses locally, reducing the need for node-external communication. However since a COMA has no back-up main memory, blocks replaced from one attraction memory must be relocated into another attraction memory. To keep memory overhead low, it is desirable to have most of the memory space filled with unique data. This leaves little space left for replication of cache blocks, resulting in that replacement traffic may become excessive. We have studied two schemes for removing the traditional demand for full inclusion between the lower-level caches and the attraction memory: the loose-inclusion and no-inclusion schemes. They differ in efficiency but also in implementation cost. Detailed simulation results show that the replacement traffic is reduced substantially for both approaches, indicating that breaking inclusion is an efficient way to bound the sensitivity for high memory pressure in COMA machines.

In flat cache-only memory architectures (COMA), an attraction-memory miss must first interrogate a directory before a copy of the requested data can be located, which often involves three network traversals. By keeping track of the identity of a potential holder of the copy–called a hint–one network traversal can be saved which reduces the read penalty. We have evaluated the reduction of the read-miss penalty provided by hints using detailed architectural simulations and four benchmark applications. The results show that a previously proposed protocol using hints can actually make the read-miss penalty larger because when the hint is not correct, an extra network traversal is needed. This has motivated us to study a new protocol, using hints, that simultaneously sends a request to the potential holder and to the directory. This protocol reduces the read-miss penalty for all applications but the protocol complexity does not seem to justify the performance improvement.

A problem with bus-based shared-memory multiprocessors is that the shared bus rapidly becomes a bottleneck in the machine, effectively limiting the machine size to somewhere between ten and twenty processors. We propose a new architecture, the bus-based COMA (BB-COMA) that addresses this problem. Compared to the standard UMA architecture, the BE-COMA has lower requirements on bus bandwidth. We have used program-driven simulation to study the two architectures running applications from the SPLASH suite. We observed a traffic reduction of up to 70% for BB-COMA, with an average of 46%, for the programs studied. The results indicate that the BB-COMA is an interesting candidate architecture for future implementations of shared-bus multiprocessors.

We study the efficiency of previously proposed stride and sequential prefetching-two promising hardware-based prefetching schemes to reduce read-miss penalties in shared-memory multiprocessors. Although stride accesses dominate in four out of six of the applications we study, we find that sequential prefetching does as well as and in same cases even better than stride prefetching for five applications. This is because 1) most strides are shorter than the block size (we assume 32 byte blocks), which means that sequential prefetching is as effective for these stride accesses, and 2) sequential prefetching also exploits the locality of read misses with nonstride accesses. However, since stride prefetching in general results in fewer useless prefetches, it offers the extra advantage of consuming less memory-system bandwidth.

We study the relative efficiency of previously proposed stride and sequential prefetching-two promising hardware-based prefetching schemes to reduce read-miss penalties in shared-memory multiprocessors. Although stride accesses dominate in four out of six of the applications we study, we find that sequential prefetching does better than stride prefetching for three applications. This is because (i) most strides are shorter than the block size (we assume 32 byte blocks), which means that sequential prefetching is as effective for stride accesses, and (ii) sequential prefetching also exploits the locality of read misses for non-stride accesses. However we find that since stride prefetching causes fewer useless prefetches, it consumes less memory-system bandwidth.>

Previous studies of bus-based shared-memo ~ multiprocessors have shown hybrid write-invalidate/write-update snooping proto-cols to be incapable of providing consistent performance improve-ments over write-invalidate protocols. In this pape ~ we analyze the deficiencies of hybrid snooping protocols under release consis-tency, and show how these deficiencies can be dramatically reduced by using write caches and read snar-ng. Our pe~ormance evaluation is based on program-driven simu-lation and a set ofjive scienti~c applications with different sharing behaviors including migratory sharing as well as producer-con-sumer sharing. We show that a hybrid protocol, extended with write caches as well as read snar-ng, manages to reduce the num-ber of coherence misses by between 83 % and 95 % as compared to a write-invalidate protocol for all$ve applications in this study. In addition, the number of bus transactions is reduced by between 36 % and 60 % for four of the applications and by 9 % for the jifth application. Because of the small implementation cost of the hybrid protocol and the two extensions, we believe that this combi-nation is an effective approach to boost the performance of bus-based multiprocessors, 1.

To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major advantage of hardware techniques is that they need no support from the programmer or compiler. Sequential prefetching is a simple hardware-controlled prefetching technique which relies on the automatic prefetch of consecutive blocks following the block that misses in the cache, thus exploiting spatial locality. In its simplest form, the number of prefetched blocks on each miss is fixed throughout the execution. However, since the prefetching efficiency varies during the execution of a program, we propose to adapt the number of pre-fetched blocks according to a dynamic measure of prefetching effectiveness. Simulations of this adaptive scheme show reductions of the number of read misses, the read penalty, and of the execution time by up to 78%, 58%, and 25% respectively.>

Coherence misses limit the performance of write-invalidate cache protocols in large-scale shared-memory multi-processors. By contrast, hybrid protocols mix updates with invalidations and can reduce the coherence miss rate. The gains of the fewer coherence misses, however, can sometimes be outweighed by contention due to the extra traffic making techniques to cut the write traffic important. We study in this paper how write traffic for hybrid protocols can be reduced by incorporating a write cache in each node. Detailed architectural simulations reveal that write caches are effective in exploiting locality in write accesses under relaxed memory consistency models. Hybrid protocols augmented with write caches with only a few entries are shown to outperform a write-invalidate protocol for all five benchmark applications under study.

Considers three simple extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with memory accesses and include a hardware prefetching scheme, a migratory sharing optimization, and a competitive-update mechanism. Since they target different components of the read and write penalties, they can be combined effectively. Detailed architectural simulations using five benchmarks show substantial combined performance gains obtained at a modest additional hardware cost. Prefetching in combination with competitive-update is the best combination under release consistency in systems with sufficient network bandwidth. By contrast, prefetching plus the migratory sharing optimization is advantageous under sequential consistency and/or in systems with limited network bandwidth.>

To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major advantage of hardware tech niques is that they need no support from the programmer or compiler. Sequential prefetching is a simple hardware-controlled prefetching technique which relies on the automatic prefetch of consecutive blocks following the block that misses in the cache. In its simplest form, the number of prefetched blocks on each miss is fixed throughout the exe cution. However, since the prefetching efficiency varies during the execution of a program, we propose to adapt the number of pref etched blocks according to a dynamic measure of prefetching effectiveness. Simulations of this adaptive scheme show significant reductions of the read penalty and of the overall execution time.

Cache memory has shown to be the most important technique to bridge the gap between the processor speed and the memory access time.The advent of high-speed RISC and superscalar processors, however, calls for small on-chip data caches.Due to physical limitations, these should be simply designed and yet yield good performance.In this paper, we present new cache architectures that address the problems of conflict misses and non-optimal line sizes in the context of direct-mapped caches.Our cache architectures can be reconfigured by software in a way that matches the reference pattern for array data structures.We show that the implementation cost of the reconfiguration capability is neglectable.We also show simulation results !M demons tratc sign i fican t performance improvements for both methods.