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Brian Totty

dblp:47/4483 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Performance modeling and evaluation · 38% Distributed systems · 16% Memory systems · 16%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking
0.011993
Communication and computation performance of the CM-5 · SC 1993
Performance modeling and evaluation
parallel performance evaluation
0.011993
Communication and computation performance of the CM-5 · SC 1993
Memory systems
data locality
0.011992
Dynamic Object Management for Distributed Data Structures · SC 1992
Distributed systems
distributed data structures
0.011992
Dynamic Object Management for Distributed Data Structures · SC 1992
Processor architecture and microarchitecture › multithreading
context switching
0.011987
Architecture of a Message-Driven Processor · ISCA 1987
Parallel and multicore computing › parallel architecture
message-passing architecture
0.011987
Architecture of a Message-Driven Processor · ISCA 1987
Interconnection networks and networks-on-chip
interprocessor communication
0.011993
Communication and computation performance of the CM-5 · SC 1993
Parallel and multicore computing › multiprocessor system
distributed-memory multiprocessor
0.011992
Dynamic Object Management for Distributed Data Structures · SC 1992

Methods — techniques the papers use, named apart from their topics

scalability assessment · 0.0benchmarking · 0.0trace-driven simulation · 0.0simulation · 0.0
YearPublicationVenuePosition
1993 Communication and computation performance of the CM-5
abstract
The Thinking Machines CM-5 is one of the first of a new generation of massively parallel systems.To assess the scalability of the CM-5's computation and interprocessor communication rates, we used a sem"es of benchmarks to measure the performance of the CM-5 data and control networks, the node vector units, and the balance of computation and communication.At the application level, we found the achievable communication bandwidth and processing rates to be roughly fifiy percent and forty percent, respectively, of the corresponding theoretical peak rates.Our early assessment is that the CM-5 is scalable but that a better balance of communication and processing rates would increase its effectiveness. 1
Thomas T. Kwan, Brian Totty, Daniel A. Reed
SC2
1992 Dynamic Object Management for Distributed Data Structures
abstract
In distributed-memory multiprocessors, remote memory accesses incur larger delays than local accesses. Hence, insightful allocation and access of distributed data can yield substantial performance gains. The authors argue for the use of dynamic data management policies encapsulated within individual distributed data structures. Distributed data structures offer performance, flexibility, abstraction, and system independence. This approach is supported by data from a trace-driven simulation study of parallel scientific benchmarks. Experimental data on memory locality, message count, message volume, and communication delay, suggest that data-structure-specific data management is superior to a single, system-imposed policy.>
Brian Totty, Daniel A. Reed
SC1
1987 Architecture of a Message-Driven Processor
abstract
We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.
William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Brian Totty, D. Scott Wills
ISCA8