Harmonic balance (HB) method is a powerful frequency-domain method used in RF circuit simulations. The key point of HB method is efficiently solving the Jacobian system in Newton’s method. In this paper, we first introduce a new time-domain preconditioner for HB Jacobian. Unlike existing time-domain preconditioners, which cannot balance the efficiency of solving the linear system corresponding to the preconditioner with the reduction in iteration step for strongly nonlinear circuit, the proposed preconditioner successfully addresses both aspects. We also present a new preconditioning method that extends time-domain preconditioners to circuit with distributed devices, which was previously unattainable. Finally, a matrix norm-based metric is proposed to measure the strength of circuit nonlinearity, which can help us a priori choose the appropriate preconditioner.

Periodic small-signal analysis is crucial but timeconsuming in RF simulation, since it may deal with many frequency points. While the Krylov subspace recycling method has greatly accelerated the simulation, the increasing memory cost in large-scale RF simulation has become a new bottleneck. A remedy for memory shortage is to restart the recycling algorithm, but may cause excessive extra iterations. To address this issue, this paper outlines a framework of recycling subspace truncation method for periodic small-signal analysis, provided with an efficient initial guess choice method and a Floquet-based subspace truncation strategy. Numerical results show that compared to the existing methods, the proposed method achieves up to $2.5 \times$ speedup in the same memory cost.

Optimizing multiple competitive black-box objectives with tight constraints poses a common challenge in analog circuit design. Multiobjective Bayesian optimization (MOBO) is a sample-efficient approach to identify the optimal tradeoffs, namely, the Pareto front (PF). However, existing MOBO methods exhibit limitations in handling high-dimensional design space, large sample budgets, many objectives and tight constraints. This article introduces VTSMOC, a sample-efficient and computationally lightweight approach for addressing high-dimensional constrained multiobjective optimization problems. VTSMOC decomposes the design space into Voronoi cells, dynamically constructing a hierarchical Voronoi tree through clustering observations with dominance relationships. Promising leaf nodes in the Voronoi tree are pinpointed by traversing the tree with gradient bandit. The diversity of PF is ensured by parallel sampling within different promising cells, selected using a diffusive strategy. We also propose the expected PF improvement (EPFI) and probability of PF improvement (PPFI) acquisition functions to facilitate the PF efficiently along the radial direction of PF surface. Compared to state-of-the-art methods, VTSMOC achieves significant improvements in both sample and computational efficiency.

As the resolution continues to increase, the scale of the power grid of the flat panel display (FPD) becomes huge. This imposes a severe computational challenge for analysis and storage. In this paper, based on the highly periodic FPD structure, we present an efficient simulator which contains a novel stamping scheme and a fast structural solver. Experiments on real industrial cases show that compared to the conventional stamping scheme, our proposed stamping scheme achieves up to 118× speedup in 74× less memory; compared to the state-of-art direct solver, Cholmod, our proposed structural solver achieves up to 17× speedup in 5× less memory.

Efficient high-dimensional performance modeling of analog/RF circuits over multiple corners is an important-yet-challenging task. In this article, we propose a novel performance modeling approach for analog/RF circuits, referred to as correlated Bayesian model fusion (C-BMF). The key idea is to encode the correlation information for both model template and coefficient magnitude among different corners by using a unified prior distribution. Next, the prior distribution is combined with a few simulation samples via Bayesian inference to efficiently determine the unknown model coefficients. Two circuit examples designed in a commercial 40-nm CMOS process demonstrate that C-BMF achieves about$2\times $cost reduction over the traditional state-of-the-art modeling technique without surrendering any accuracy.

Graph spectral sparsification-based preconditioning technique has shown promising results for power grid analysis. However, the conventional methods converge slowly for high-accuracy requirement. In this work, we propose an efficient approach to address this issue. Instead of using the Cholesky factorization, we employ the incomplete Cholesky factorization to factorize the spectral sparsifier. We also propose a concept of graph spectral pattern, which can further reduce the preconditioned conjugate gradient (PCG) iterations using less number of nonzeros. Experiments show that under 10−6 relative tolerance, our proposed preconditioning technique achieves$1.17\times $speedup compared to AMGPCG in average; compared to the conventional spectral sparsification-based preconditioning techniques, our proposed approach achieves up to$8.53\times $speedup of the factorization,$8.74\times $speedup of the PCG iteration, and$5.6\times $speedup of the total time. Moreover, the speedup of the total time continues to enlarge for higher-accuracy requirement, e.g., 10−12. Finally, but not least, our method is compatible with existing graph spectral sparsification algorithms for power grid analysis.

In this article, to accurately estimate the rare failure rates for large-scale circuits (e.g., SRAM) where process variations are modeled as truncated normal distributions in high-dimensional space, we propose a novel truncated scaled-sigma sampling (T-SSS) method. Similar to scaled-sigma sampling (SSS), T-SSS distorts the truncated normal distributions by a scaling factor, resulting in an analytical model for failure rate estimation. By drawing random samples from the distorted distribution and estimating a sequence of scaled failure rates, we can solve all unknown model coefficients and predict the original failure rate by extrapolation. The accuracy of T-SSS is further assessed by estimating its confidence interval (CI) based on resampling. Our numerical results demonstrate that the proposed T-SSS method can achieve superior accuracy over the state-of-the-art method without increasing the computational cost.

In this article, a novel asymptotic probability evaluation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. An error refinement method based on look-up table is further developed to improve numerical stability and, hence, reduce estimation error. Furthermore, a statistical algorithm based on resampling is developed to accurately estimate the confidence interval of APE. Our numerical experiments demonstrate that compared to the state-of-the-art method, APE can reduce the estimation error by up to$30\times $without increasing the computational cost.

In this paper, we propose an efficient parametric yield estimation method based on Bayesian Inference. By observing that nowadays analog and mixed-signal circuit is designed via a multi-stage flow, and that the circuit performance correlation of early stage and late stage is naturally symmetrical, we introduce a general region to capture the common features of the early and late stage. Meanwhile, two private regions are also incorporated to represent the unique features of these two stages respectively. Afterwards, we introduce classifiers one for each region to explicitly encode the correlation information. Next, we set up a graphical model, and consequently adopt Bayesian Inference to calculate the model parameters. Finally, based on the obtained optimal model parameters, we can accurately and efficiently estimate the parametric yield with a simple sampling method. Our numerical experiments demonstrate that compared to the state-of-the-art algorithms, our proposed method can better estimate the yield while significantly reducing the number of circuit simulations.

To efficiently estimate parametric yields over multiple process, voltage, temperature corners for binary output circuits, we propose a novel Bayesian Inference method based on Bernoulli distribution with conjugate prior in this paper. The key idea is to adopt a product of Beta distributions as the conjugate prior for the yields and encode circuit performance correlations among different corners into this prior. Next, the hyper-parameters are optimized by using multi-start Quasi-Newton method, and the yields over different corners are estimated via maximum-a-posteriori. Two circuit examples demonstrate that the proposed method achieves up to 3.0× cost reduction over the state-of-the-art methods without surrendering any accuracy.

Acceleration and wide deployability in deeper recurrent neural network is hindered by high demand for computation and memory storage on devices with memory and latency constraints. In this work, we propose a novel regularization method to learn hardware-friendly sparse structures for deep recurrent neural networks. Considering the consistency of dimension in continuous time units in recurrent neural networks, low-rank structured sparse approximations of the weight matrices are learned through the regularization without dimension distortion. Our method is architecture agnostic and can learn compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The structured sparsity rather than random sparsity also facilitates the hardware implementation. Experiments on language modeling of Penn TreeBank dataset show that our approach can reduce the parameters of stacked recurrent neural network model by over 90% with less than 1% perplexity loss. It is also successfully evaluated on larger highway neural network model with word2vec dataset like enwik8 and text8 using only 20M weights.

In this article, we propose an efficient correlated Bayesian inference (CBI) method to estimate the system-level failure rates for large-scale circuit systems over multiple process corners. The key idea is to encode the correlations of circuit performances among the different corners into the prior distributions of several carefully defined failure events. The hyper-parameters of these distributions can be learned from a few simulation samples via Bayesian inference and, next, the system-level failure rates over different corners can be simultaneously estimated by taking into account these prior distributions. An iteratively constrained inference method is further developed to guarantee the numerical stability of the proposed method and legalize all estimated failure rates. The numerical experiments demonstrate that compared to the state-of-the-art algorithm, the proposed method can achieve around 10× runtime reduction without surrendering any accuracy.

In this article, a novel asymptotic probability approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient hierarchical subset simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimate the overall failure rate of correlated rare failure events involving more than 20 000 independent random variables.

Tunable analog/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are developed by using real-valued performance metrics. However, when measuring a performance of interest on silicon, it is often substantially more expensive to obtain a real-valued measurement than a binary testing outcome (i.e., pass or fail). In this article, we propose a Gaussian Process Classification model to capture the binary performance metrics of tunable analog/RF circuits. Based on these models, post-silicon programming is cast into an optimization problem that can be solved by a novel Bayesian optimization algorithm. Moreover, measurement noises are further incorporated into our proposed post-silicon programming to produce a robust circuit. Two circuit examples demonstrate that the proposed approach can efficiently program tunable circuits with binary performance metrics while other conventional methods are not applicable.

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, we use a single BNN to simultaneously model multiple performances of interest (PoIs) of an analog circuit. This BNN model can be trained by using a novel automatic differential variational inference (ADVI) method with affordable computational cost. Next, the performance trade-off model can be extracted by embedding BNN into Bayesian optimization framework combined with a modified multi-objective evolutionary method. Since the correlations among different PoIs are implicitly encoded in the BNN model, the proposed method can capture the performance trade-off model efficiently and accurately. The numerical experiments demonstrate that compared to the state-of-the-art algorithms, the proposed method can achieve up to 2× runtime reduction without surrendering any accuracy.

In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work.

Automated analog circuit design is promising for increasing the design productivity and narrowing the time-tomarket, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm quite smart in a way that the overall optimization process is self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experiments have demonstrated that the proposed smart-MSP is 2.6-12.5× faster than the original MSP method, and is 1.3-2100× faster than other state-of-the-art methods.

In this paper, a novel Asymptotic Probability Estimation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. An error refinement method based on Look-up Table (LUT) is further developed to improve numerical stability and, hence, reduce estimation error. Our numerical experiments demonstrate that compared to the state-of-the-art method, APE can reduce the estimation error by up to 45x without increasing the computational cost.

In this paper, a novel Asymptotic Probability Approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key idea of APA is to approximate the overall circuit failure rate based on a set of carefully defined failure events. An efficient Hierarchal Subset Simulation (H-SUS) method is developed to calculate the aforementioned failure rate and a statistical methodology is further proposed to estimate the confidence interval of APA. Our numerical experiments demonstrate that APA can accurately and reliably estimates the overall failure rate of correlated rare failure events involving more than 20,000 independent random variables.

This paper presents a fast compressive sensing reconstruction algorithm implemented on FPGA using Orthogonal Matching Pursuit (OMP). The algorithm is optimized with QR decomposition to solve the least square problem and avoids the square root operations to facilitate the hardware implementation. The implementation results show that this design can run at a frequency of 100MHz and the proposed algorithm achieves 50% lower complexity than the other existed algorithms.

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.

In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip spatial variations recovery at extremely low measurement cost. Applying this method, HMT is introduced to set up a statistical model for coefficients after exploring the underlying correlated representation of the spatial variation in the frequency domain. Accordingly, two key inherent properties of the modeling coefficients, i.e., correlations and sparse presentations in the frequency domain, can be captured exactly and the modeling accuracy can be improved evidently. Then, maximum-a-posteriori estimation is applied to formulate the original problem as a convex optimization that could be solved efficiently and robustly. Numerical results based on industrial data demonstrate that the proposed method can achieve superior accuracy over other existing approaches including orthogonal matching pursuit, l1-norm regularization, and reweighted l1-norm regularization.

Simulation of power girds has become increasingly computationally expensive. In this paper, we propose a Model Order Reduction (MOR) method for power grid circuits by extending the existing Aggregation-based MOR (AMOR) method. In the proposed method, besides resistors and capacitors, current sources are also aggregated to improve MOR efficiency. Moreover, pre-partition and parallelization techniques are employed to decrease the reduction time. Numerical results demonstrate that the reduced-order models can achieve up to 18× simulation speed-up over the original circuits without much loss of accuracy.

In this paper, we propose an efficient Aggregating based Model Order Reduction method (AMOR) for many-terminal interconnect circuits. The proposed AMOR method is based on the observation that those adjacent nodes of interconnect circuits with almost the same voltage can be aggregated together as a "super node". Motivated by such an idea, we propose an efficient spectral partition algorithm in AMOR method to partition the nodes into groups with almost the same voltages. The reduced-order models are then obtained by aggregating the adjacent nodes within the same groups together as "super nodes" in AMOR method. The efficiency of AMOR method is not limited by the numbers of the terminals of the networks. Moreover, noticing that the aggregating procedure can be regarded as mapping the original problem into a coarse-grid problem in multigrid method, we propose a computation-efficient smoothing procedure to further improve the simulation accuracy of the reduced-order models. With such a strategy, the simulation accuracy of the reduced-order models can always be guaranteed. Numerical results have demonstrated that, without the smoothing procedure, the reduced-order models obtained by AMOR can still achieve higher simulation efficiency in terms of accuracy and CPU time than the reduced-order models obtained by the existing elimination based methods. With the smoothing procedure, the simulation accuracy of the reduced-order models can further be improved with several iterations.

Trajectory piecewise-linear macromodeling (TPWL) technique has been widely employed to characterize strong nonlinear circuits, and makes the reduction of the strong nonlinear circuits possible. The trajectory piecewise-linear macromodeling technique linearizes nonlinear circuits around multiple expansion points which are extracted from state trajectories driven by training inputs. However, the accuracy of the trajectory piecewise-linear macromodeling technique heavily relies on the extracted expansion points and the training inputs. It will lead to large error in simulation if state vector reaches regions far away from the extracted expansion points. In this paper, we propose an efficient transistor-level piecewise linearization scheme for macromodeling of nonlinear circuits. Piecewise linear models are first built for each transistor. The macromodel of the whole nonlinear circuit is then constructed by combining all the piecewise-linear models of the transistors together with appropriate weight functions. The proposed approach can cover remarkably larger state space than the TPWL method. By using the complete piecewise-linear models of the transistors, the constructed piecewise-linear models of the nonlinear circuits are capable of covering the whole state space of the nonlinear circuits. More importantly, model order reduction of the proposed transistor-level piecewise linearization macromodel is also possible, which makes the proposed method a potentially good macromodeling approach for model order reduction of nonlinear circuits.

This paper presents a multiparameter moment-matching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process (TAP). It is referred to as a Parameterized Interconnect Macromodeling via a TAP (PIMTAP) algorithm. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive. PIMTAP model yields the same form of the original state equations and preserves the passivity of parameterized RLC networks like the well-known method passive reduced-order interconnect macromodeling algorithm for nonparameterized RLC networks.

In this paper, stochastic collocation algorithm combined with sparse grid technique (SSCA) is proposed to deal with the periodic steady-state analysis for nonlinear systems with process variations. Compared to the existing approaches, SSCA has several considerable merits. Firstly, compared with the moment-matching parameterized model order reduction (PMOR), which equally treats the circuit response on process variables and frequency parameter by Taylor approximation, SSCA employs homogeneous chaos to capture the impact of process variations with exponential convergence rate and adopts Fourier series or wavelet bases to model the steady-state behavior in time domain. Secondly, contrary to stochastic Galerkin algorithm (SGA), which is efficient for stochastic linear system analysis, the complexity of SSCA is much smaller than that of SGA for nonlinear case. Thirdly, different from efficient collocation method, the heuristic approach which may results in "rank deficient problem" and "Runge phenomenon", sparse grid technique is developed to select the collocation points in SSCA in order to reduce the complexity while guaranteing the approximation accuracy. Furthermore, though SSCA is proposed for the stochastic nonlinear steady-state analysis, it can be applied for any other kinds of nonlinear system simulation with process variations, such as transient analysis, etc.

This paper presents a multiparameter moment- matching based model order reduction technique for parameter- ized interconnect networks via a novel two-directional Arnoldi process. It is referred to as a PIMTAP algorithm, which stands for Parameterized Interconnect Macromodeling algorithm via a Two-directional Arnoldi Process. PIMTAP inherits the advan- tages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive, and preserves the passivity of parameterized RLC networks.

This paper aims to explore RLC equivalent circuit synthesis method for reduced-order models of interconnect circuits obtained by Krylov subspace based model order reduction (MOR) methods. To guarantee pure RLC equivalent circuits can be synthesized for the reduced-order models, both the structures of input and output incidence matrices and the block structure of the circuit matrices should be preserved in the reduced-order models. Block structure preserving MOR methods such as SPRIM (Freund, 2004) and SAPOR (Su et al., 2004) have been well established. In this paper, an embeddable input-output structure preserving order reduction (IOPOR) technique was proposed to further preserve the structures of input and output incidence matrices in the reduced-order models. By combining block structure preserving MOR methods and IOPOR technique, an RLC equivalent circuit synthesis method RLCSYN (RLC SYNthesis) was developed. Inline diagonalization and regularization techniques are specifically proposed to enhance the robustness of inductance synthesis. The pure RLC model, high modeling accuracy, passivity guaranteed property and SPICE simulation robustness make RLCSYN more applicable in interconnect analysis, either for digital IC design or mixed signal IC simulation.

In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reduction approach can achieve smaller reduced order circuits with very high accuracy, especially for those circuits with strong singularities. Furthermore, to compute the basis function coefficient vectors, a fast Sylvester equation solver is proposed, which works more than one or two orders faster than the vector equation solver employed by Chebyshev reduction method. The proposed wavelet method is also compared with the frequency domain model reduction method, which may loose accuracy in time domain. Both theoretical analysis and experiment results have demonstrated the high speed and high accuracy of the proposed method.

With the development of IC technology, it becomes urgent to investigate model reduction method for interconnects with process variations. In this paper, a one-shot projection algorithm (OPM) is proposed to generate a projection matrix that is independent of statistically varying parameters. As a result, construction of the reduced system can be decoupled with the Monte Carlo analysis in either frequency domain or time domain. Therefore, without loss of accuracy, OPM can obtain a reduced system in much less CPU time compared with the previous perturbation scheme. Numerical results have demonstrated the advantages of the proposed OPM

Recently model order reduction techniques for second-order systems have obtained many research interests for the simulation of RCS interconnect circuits employing susceptance elements. In this paper, we propose a Block SAPOR (Block Second-order Arnoldi method for Passive Order Reduction) for Multi-Input Multi-Output RCS Circuits. The proposed Block SAPOR algorithm can simultaneously guarantee passivity and achieve higher accuracy than the first order reduction technique PRIMA. Most importantly, the reduced system matrices obtained by the proposed method can preserve the structure of the original system matrices. Such a nice property makes it possible to construct an equivalent RCS circuit for the reduced system.

The recently-introduced susceptance element exhibits many prominent features in modeling the on-chip magnetic couplings. For an RCS circuit, it is better to be formulated as a second-order system. Therefore, corresponding MOR (model-order reduction) techniques for second-order systems are desired to efficiently deal with the ever-increasing circuit scale and to preserve essential model properties. We first review the existing MOR methods for RCS circuits, such as ENOR and SMOR, and discuss several key issues related to numerical stability and accuracy of the methods. Then, a technique, SAPOR (second-order Arnoldi method for passive order reduction), is proposed to effectively address these issues. Based on an implementation of a generalized second-order Arnoldi method, SAPOR is numerically stable and efficient. Meanwhile, the reduced-order system also guarantees passivity.