Demo Data from EDBT 2026 / reviewers in the wild / expert
William A. Nazaret
dblp:47/4599
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 50% Integrated circuit design · 25% Electronic design automation · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1992 | Integrated circuit design optimization using a sequential strategy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation
design optimization |
0.0 | 1 | 1992 | Integrated circuit design optimization using a sequential strategy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Performance modeling and evaluation › simulation
simulation-based design |
0.0 | 1 | 1992 | Integrated circuit design optimization using a sequential strategy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Performance modeling and evaluation
stochastic modeling |
0.0 | 1 | 1992 | Integrated circuit design optimization using a sequential strategy · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
stochastic process modeling · 0.0sequential experimentation · 0.0CAD simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Integrated circuit design optimization using a sequential strategyabstractThe authors describe a sequential strategy for designing manufacturable integrated circuits using available CAD tools. Optimizing the performance of complex designs in the presence of unwanted parameter variations can take a prohibitively large number of computer runs. These methods overcome this complexity by combining sequential experimentation with modeling of the CAD simulator output as realizations of stochastic processes. These models give inexpensive approximations that enable location of subregions on which to continue the search for the optimal design. The multistage experimentation reduces the number of simulation runs required to obtain sufficiently accurate approximations. The strategy is able to treat circuits with many parameters, performances, and criteria. Included are two examples where improved designs have been found by these methods. The first is a zero-temperature-coefficient current reference IC. The second is a gallium arsenide voltage level shifter IC with multiple performances of interest.> Maria C. Bernardo, Robert J. Buck, Lihsin Liu, William A. Nazaret, Jerome Sacks, William J. Welch |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |