In this paper, we propose a CMOS current comparison circuit operating at cryogenic temperature to readout spin quantum bit (qubit) states via a charge sensing scheme. A current integrator and correlation double sampling circuit are implemented in the proposed current comparator since precise current sensing is required to achieve readout the states of qubits. The measurement results indicate the feasibility that the reduced readout time by a factor of 1/100 and 100-times better current resolution with the readout fidelity of 99.9 % compared to the conventional readout systems are achieved. Additionally, the current and noise specifications for a charge sensor required to attain it are discussed. Furthermore, the proposed current comparator attains the best tradeoff among power, current resolution, and readout time, compared with the conventional cryogenic current readout circuits.

We implemented pseudo-linear feedback shift-register-based physical unclonable functions (PL-PUFs) on silicon and analyzed their performances in terms of reproducibility, uniqueness, and resistance to machine-learning attacks. A PL-PUF is compact and high-throughput PUF, slightly oversensitive to voltage fluctuations. To overcome this drawback, we developed a capturing signal generation circuit that was tolerant to the reproducibility degradation caused by supply voltage changes. We also implemented a Built-In Self-Test (BIST) circuit with an irreversible destruction mechanism to enable exceedingly fast challenge–response pairs (CPRs) for the PUFs before shipping. After the CPRs were evaluated, the BIST circuit became invulnerable to exploitation by attackers.

In this study, we demonstrate the first implementation of a pseudo linear feedback shift register physical unclonable function (PL-PUF) on silicon, and a proposal of the power supply design to obtain fine reproducibility. Unlike SRAM PUFs, a PL-PUF can generate responses without memory cells, and therefore is secure against attacks extracting internal memory values. We design a capturing signal-generation circuit that brings tolerance to the degradation of reproducibility due to supply voltage change, and implement PL-PUF on 65nm CMOS process. Implemented PL-PUF achieves fine reproducibility (μ=1.09-10.52% fractional HD) and uniqueness (μ=49.01-49.56%, σ=5.38-5.77% class-to-class HD, 0.983-0.941 entropy) on silicon.

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.

This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. The strength of the keeper device is controlled by the differential gate voltage, which guarantees low gate-source voltage at the beginning of the evaluation phase and high gate-source voltage during rest of the time.

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by intrinsic within-die variation is proposed. The timing variation is reduced by selecting an appropriate configuration for each chip from a set of independent configurations, the critical paths of which do not share the same circuit resources on the FPGA. In this article, the actual method used to generate independent multiple configurations by simply repeating the routing phase is shown, along with the results of Monte Carlo simulation with 10,000 samples. One simulation result showed that the standard deviations of maximum critical path delays are reduced by 28% and 49% for 10% and 30% V th variations ( σ/ μ ), respectively, with 10 independent configurations. Therefore, the proposed method is especially effective for larger V th variation and is expected to be useful for suppressing the performance variation of FPGAs due to the future increase of parameter variation. Another simulation result showed that the effectiveness of the proposed technique was saturated at the use of 10 or more configurations because of the degradation of the quality of the configurations. Therefore, the use of 10 or fewer configurations is reasonable.

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

First prototype flex power FPGA chip is presented. Basic concept of flex power FPGA is to control speed/power trade-off relationship flexibly by assigning the proper threshold voltage generated from body-bias control circuits to transistors. An experimental chip, which implements a power configurable block array connected in series having minimal indispensable functions to flex power FPGA, i.e. circuit configurability and power configurability, was fabricated in 90 nm standard CMOS technology with triple-well option for the first time. As evaluation results of the static power saving ability and operating speed controllability, the concept of flex power FPGA is proved.

Flex Power FPGA can flexibly control the operating speed and power consumption by flexible assignment of the threshold voltage to transistor. This paper evaluates the static power consumption and area overhead on various threshold voltage control granularity in the Flex Power FPGA based on specific settings. There is the trade-off relationship between static power and area overhead in threshold voltage control granularity in Flex Power FPGA with bulk MOS transistors. Moreover, division of the threshold voltage controlled transistor area has a big influence on the trade-off. For example of evaluation results, static power reduces less than 1/5 of original level, while increase an area overhead of less than 40% by appropriately dividing the threshold voltage controlled transistor areas. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.

In a traditional 2-D field-programmable gate array (FPGA), the number of routing switches increases as the number of logic gates increases, and thereby causes a decrease in the logic density. DeHon et al. demonstrated that a tree-based FPGA they proposed resolves this problem and requires only a constant number ofswitches per gate without any relation to the total number of gates. This paper presents that a multidimensional FPGA that exploits the multidimensional mesh topology also achieves asymptotically identical area efficiency to that of a tree-based FPGA. We model a multidimensional FPGA as a simple extension of the traditional 2-D and 3-D FPGAs, and realize it by embedding it onto a 2-D chip. We show a multidimensional FPGA can be embedded onto a 2-D chip with no critical increase in the amount of metal wiring. Although our embedding method causes a gap between the lengths of wire segments in different axial directions, a multidimensional FPGA indicates lower interconnection delay than a 2-D FPGA. We show that the speed advantage of a 4-D FPGA compared with a 2-D FPGA extends along with further integration and scaling of semiconductor devices by predicting maximum and average net delays.

The flex power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the flex power FPGA. There is also a trade-off relationship between the static power consumption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained

An FPGA with field-programmable Vthcomponents can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (Vth) of transistors. Since Vthfor transistors for a specific circuit block in an FPGA is chosen from a set of Vthvalues defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable Vthmethod. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable Vthcomponents was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-Vthtransistor in a BBVS reveals that deep reverse body bias for high-Vthtransistor does not necessarily offer the optimal condition, and optimization is necessary

The Flex Power FPGA design is presented as a novel FPGA design offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This design targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This design is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.

No abstract available.

Multi-threading is often used to compile logic and functional languages, and implement parallel C libraries. Fine-grain multi-threading requires rapid context switching, which can be slow on architectures with register windows. In past, researchers have either proposed new hardware support for dynamic allocation of windows to threads, or have sacrificed fast procedure calls by fixed allocation of windows to threads.