This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has Ronincreased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has Ronincreased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.

This paper presents an on-chip pulse signaling scheme for low power on-chip interconnection. Both near-end and far-end employ equalization circuits to compensate the high frequency attenuation of long channel. The on-chip data bus is designed by co-planar micro-strip line in Metal 5 and Metal 6 and with a characteristic impedance of 75 ohm. The receiver uses self-biased inverters and transmission gates to design inductive-peaking and non-clock hysteresis amplifiers. In 0.13um CMOS process, the proposed I/O occupies a total area of 0.07mm2. At a bit rate of 5Gbps, the accumulated peak-to-peak jitter of overall I/O system and a 5mm of channel length is 76ps. And it consumes 8mW of power under 1.2V supply voltage or with a power efficiency of 0.32pJ/bit/mm.

For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.

A novel prediction scheme is proposed for real-time MPEG video to predict the burst and long-range dependent traffic. The trend and periodic characteristics of MPEG video traffic are fully captured by a proposed stochastic state-space dynamic model. Then a recursive Hinfinfiltering algorithm is proposed to estimate traffic for long-range prediction. Simulation results based on real MPEG traffic data show that the proposed scheme has superior performance and lower complexity than some adaptive neural network methods, such as TDNN, NARX, and Elman neural networks.

This paper proposes an RF test and diagnosis methodology based on digital DFT structure and built- in DSP function of a SoC Chip. Constellation variation plots are proposed to identify the faulty component. Furthermore, linear interpolation is used to determine the amount of variation. The simulated test results show that the method is able to identify not only the faulty component but also the variation amount precise.

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.

We propose an interconnect diagnosis scheme based on oscillation ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution.

In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small

For automobile industry, rubber is widely used for noise isolation and vibration reduction. However, due to its distributed and nonlinear characteristics, it is hard to precisely estimate its characteristics such as the loss coefficient which is defined as the tangent of the phase delay between the fundamental components of the strain and the stress under sinusoidal driving. Moreover, even using a truncated finite-dimensional model, with rubber's nonlinearity, resonance of the testing mechanical system, and measurement noise, optimal estimation of the loss coefficient by using Kalman filter is not feasible in the presence of these uncertainties and non-Gaussian disturbances. Therefore, Hinfinfilter is applied in this paper to robustly estimate the loss coefficient from the state-space perspective. As a state-space model for representing a sinusoidal signal has eigenvalues on the unit circle, the measured data is first processed by imposing a suitable exponential decay in order to ensure the stability of the Hinfinfilter. Moreover, due to finite data length, an iterative Hinfinfilter is developed to improve the accuracy of parameter estimates. At each iteration, estimation of disturbances by using the Hinfinfilter is first performed by applying the previously estimated components of the desired signal. Then a robust estimation of the desired signal is made with respect to the measured signal which is subtracted by the estimated disturbance. Both simulation study and experimental test are conducted to verify the performance of the proposed iterative Hinfinfilter.

An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution

We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.

In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.

The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied, considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.

This paper proposes a novel voltage measurement technique for LCD driver testing by the use of logic test channel of an ATE. The method is able to achieve less than 1mV error with the presence of 32mV RMS noise.

On-line quiescent state monitoring is achieved by utilizing dual comparators compatible with the IEEE 1149.4 standard analog DFT. Statistical analysis is used to minimize the impacts of dynamic signals and noise carried in the signal line. The experimental results confirm the mathematical analysis and assure the test methodology.

A self calibrated BIST methodology is proposed to overcome the process variation of the BIST circuitry. Two test methods are proposed, one by statistical analysis and another by curve fitting. Test hardware is built by discrete components to emulate the ADC BIST circuitry. Experimental results verify the feasibility of the methodology.

An integrated memory test system is presented. It includes a reconfigurable memory test module, a test algorithm editor, a memory fault simulator, and a test code generator. For a given memory organization, fault list, and test algorithm, the system automatically reports the fault coverage, generates control assembly codes, and produces circuit net list for test pattern generation. The system has been implemented in 9000 lines of C++ program based on the Microsoft Windows graphic user interface. It has been verified on different test algorithms and memory chips.

Three-state drivers are modified to exhibit wired-logic properties in test mode. It does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

A DSP based methodology to generate compensative stimuli is proposed to remove the parasitic effects in analog test buses. Experiments, using HSPICE simulation, show that the differences between stimuli and ideal signal are less then 1% with only 64 sample points.

A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. The intrinsic response extraction cross-checks and cancels the parasitic effects of both test application and response observation paths. The tests using both SPICE simulation and MNABST-1 P1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. Furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.

In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers (OP) is demonstrated and presented. The methodology at first presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. An application of the derived models to Monte Carlo simulation to save computation time is also demonstrated.

This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.

In this work, IDDQ current for deep submicron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1/spl times/10/sup 7/ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep submicron VLSI for the next ten years.

This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers, and wires. The crosstalk profile is plotted by monitoring the changes in delay with the presence of the crosstalk. The distinguished features include all digital design and low hardware overhead. The SPICE simulation results prove the feasibility of the methodology.

A DSP based test methodology is proposed to remove the parasitic and crosstalk effects, the two major drawbacks when using the analog buses. Experiments, using SPICE simulation and real measurement data show a significant improvement over the direct measurement.

The removal of the parasitic effects is an emerging issue in the implementation of the IEEE standard 1149.4 analog test buses. For this, this paper defines the intrinsic response and derives an extraction algorithm. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effect. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects. The test results using SPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects and the variations in the test signals. The proposed methodology is further tested in the real measurement using the MNABST-1 test chip designed by Matsushita/Panasonic and provided by 1149.4 Working Group. The test results show that the intrinsic response has an improvement of 15.4 dB in signal-to-noise ratio as compared to the direct measurement. It also extends the test frequency range by an order of magnitude. Both tests reassert that the intrinsic response is independent of parasitic effects and input signal variation. They also show that the proposed extraction algorithm is robust enough to handle not only the parasitic effects but also the noise in the real measurement environment.

In this paper an analog metrology and test stimulus selection guidelines are proposed based on the frequency domain analysis of the stimulus and the CUT. To show the feasibility, a 4th order leapfrog filter and a DSP deconvolution operation are used as the test vehicle. The experimental results on the real measured data show that the increase in observation periods can effectively compensate the increase in the environment noise.

This paper presents a metrology to extend P1149.4 from external component testing to internal module measurement. A series of experiment has been conducted to verify that the metrology is able to tolerate parasitic effects and test signal variation. As compare to the direct measurement, the metrology achieves an improvement of 14 dB in measurement SNR. Furthermore, it also extends the frequency range by one order.

Comprehensive interconnect BIST achieves 100% fault coverage on net faults and driver faults without any prerequisitive assumption on the connection configuration and the fault-free and faulty behavior of the interconnects. Guidelines are derived and structure maps are proposed to achieve the goal.

A linear optimal test generation algorithm is proposed to decompose serial test vectors into segments with one for each driver.Each driver is assigned a serial vector with t~vo or more transitions for the detection of net and driver faults.As compared to the conventional counting and transition sequences, the reduction is up to 20% for buses and 36% for general networks.

The interconnect BIST is achieved by the on-line polling for the composite vectors that contain the encoded information, for the test generation and response evaluation on selective drivers and receivers to adapt to the changing configuration.

ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization, and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.

Signal reconstruction reconstructs a multiple period low-rate sampled waveform into a one-period high-rate sampled waveform. With which, we are able to provide sufficient samples of analog signals for DSP based testing using on-chip ADCs. Test results show that a 128-sample-per-period waveform can be reconstructed from a 2.4 samples per period waveform sampled by a 20 MHz 8-bit ADC.

An intrinsic response extraction algorithm is derived and implemented to remove the parasitic effects in P1149.4 analog measurement. The methodology is tested on and verified by SPICE simulation results and real measurement data.

In this paper, we present a syndrome test methodology for the testing of unscanned interconnects in a boundary scan environment. Mathematical equations are derived for the relationship of test length, fault-free and faulty syndromes, and tolerable error rate. To calculate fault-free and faulty syndromes, we propose an event driven syndrome simulation algorithm. To shorten testing time and reduce test cost, we transform and solve the problem as a set covering problem.

In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.

In this paper, a functional fault model for analog circuit diagnosis is proposed. A faulty module is modeled as a fault-free module in serial or in parallel with a fault module. To extract such a fault module, we adopt an iterative deconvolution technique to deconvolute the impulse response of the fault module from the faulty response. The test results show that with such a fault model and fault extraction technique the diagnostic resolution is improved significantly due to the separation of the fault and the system function. Moreover, such a fault model allows single-module fault tables to be applied to the diagnosis of a multi-module system.

In this paper, PMOTA, a parallel event-driven relaxation-based algorithm for the timing simulation of MOS circuits, is proposed. Two new schemes, static data distribution and dynamic event assignment, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilization and balanced load among processor elements. Implementation results show that parallel simulations on distributed memory multiprocessor are feasible for large scale circuit simulation.

A methodology and integrated system for the optimization of integrated circuits is presented. We propose the method that combines the symbolic analyzer and effective optimization algorithms to shorten the computation time. After selecting a circuit topology, the symbolic simulator SAGA2 is invoked to model the circuit. SAGA2 generates exact analytic expressions which describe the circuit's behavior. The model is then passed to the design optimization program. The optimization program sizes all elements to satisfy the performance constraints and a user-defined design objective. A forms-based user interface is provided to allow the designer to specify the problem easily. The system had been applied in the filter circuit design.

A hierarchical symbolic analyzer (SAGA2) for the analysis of electronic circuits is presented. SAGA2 analyzes lumped, linear, or linearized (small-signal) circuits in the S- and Z-domain. For large circuits, a hierarchical two-port method is used that is two to three order faster than that without using the hierarchical method. Also, the memory used is dramatically reduced.>

An I/sub DDQ/ based scheme has been presented for concurrent built-in self-test of MCM interconnects. The scheme detects interconnect faults while the system is on-line.

This paper presents a serial scan test vector compression methodology for the test time reduction in a scan-based test environment. The reduction is achieved by the overlapping of two consecutive vectors. Hence, the order of test vectors determines the amount of reduction in tiem. Here, two test vector ordering algorithms, depth first greedy and coalesced simple orders algorithms, have been derived, implemented, and tested. Experimental results obtained are very close to estimations by statistical analysis.>

The HPath algorithm for multiple-path sensitization in hierarchical, multilevel descriptions, which is based on semiregular structures within many VLSI circuits, is discussed. The algorithm which has been derived, implemented, and tested is applicable to circuits which can be described as semiregular and pseudocombinational for performance of testing functions related to test pattern generation, design-for-testability, built-in self-test, and diagnosis. HPath sensitizes the target paths, which may consist of multiple bits, one by one through hierarchically described circuits. Depending on the specification of each path, HPath propagates the path block by block in either the forward or backward direction. HPath is, in fact, a control mechanism which determines which path to sensitize and which block to propagate through. The sensitization is actually done by its two major components, GPath and FPath. GPath is an implicit enumeration algorithm which utilizes symbolic manipulation to achieve multiple-path sensitization for gate-level circuits. FPath is a rule-based subsystem which sensitizes multiple paths for functional-level descriptions through a sequence of rule applications. It is shown that GPath is not as efficient as FPath.>

The authors propose a special class of hierarchy, the sensitizable hierarchy, to handle simultaneously both circuit partitioning and test pattern delivery for pseudoexhaustive BIST (built-in self-test). Instead of developing specialized tools for different cases in an unsensitizable hierarchy, they attempt to reconstructure the hierarchy to make it sensitizable. In order to verify the sensitizability of a hierarchy and restructure an unsensitizable hierarchy, the authors study the characteristics of hierarchical circuits and conclude that there are three usable semiregular properties, namely, the separation of data and control signals, the availability of functional units and functional descriptions, and frequent use of array structure. On the basis of these properties, the following are derived: a structure recognition process to identify the implicit array and functional unit structure; a hierarchical, multilevel, multiple-path sensitization algorithm to sensitize paths for test application and response observation; a restructuring process to obtain a sensitizable hierarchy; and a straightforward procedure for pseudoexhaustive BIST for a sensitizable hierarchy. All of these processes and procedures use a common knowledge base and are integrated by use of a frame-based system implemented with Franz Lisp.>