Using functional test for Fmaxanalysis is still the only effective method used in practice in spite of the fact that the test cost associated with functional Fmaxtest remains to be a major problem. In this paper, we develop novel design-for-testability (DFT) structures to considerably reduce the cost of initializing the circuit during functional test. The proposed architectures take advantage of existing DFT structures to reduce the overall cost of hardware and have no impact on the circuit timing. Our implementations of these DFT structures for initializing ITC'99 benchmark circuit b19 demonstrate the effectiveness of these techniques in reducing test time and thus the overall test cost.

Starting from an analysis of the accomplishments and shortcomings of the existing approaches, this paper proposes a new description language able to satisfy all the requirements of IJTAG while providing a fresh and sound base for future evolutions.

In this paper, we present a boundary scan based system test approach for large and complex electronic systems. Using the multi-drop architecture, a test bus is extended through the backplane and the boundary scan chain of every board is connected to this test bus through a gateway device. We present a comprehensive system test method using this test architecture to achieve high quality, reliability and efficient diagnosis of structural defects and some functional errors. This test architecture enables many advanced test methods like, embedded test application for periodic system maintenance, high quality backplane test for efficient diagnosis of structural defects on the backplane, in-system remote programming of programmable devices in the field. Finally, we present a novel fault injection method to detect and diagnose various functional errors in the system software of an electronic system. These methods were implemented in various systems and we present some implementation data to show the effectiveness of these advanced test methods.

As electronic systems are becoming more complex with higher performance and require higher reliability, system test is becoming a very challenging task. Traditionally, functional test has been used to detect various design and manufacturing defects for electronic systems. However, functional test doesn’t work efficiently for large and complex systems specially when debugging and diagnosis of failure conditions is targeted. Boundary scan based test technology is being used for testing circuit boards in the industry for over a decade after being standardized by IEEE. This technology provides an access path to all the pins on all boundary scan-able chips on a circuit board.

A novel fault injection (a.k.a. fault insertion) method to facilitate the development of high quality system test is presented in this paper In this method, we utilize the existing boundary scan (BS) architecture of an FPGA to inject a hardware fault condition at any pin of the FPGA on a circuit board. Existing user-defined instructions of most FPGA BS architectures and the newly proposed design of their corresponding user-defined scan registers (USRs) constitute the proposed fault injection architecture. No new instruction, and no modification of the existing test access port (TAP) controller and BS registers are required. In addition, it is possible to reconfigure where and what type of faults to be injected asynchronously via the BS architecture while the system is online. Although the proposed method incurs at least additional delay through a multiplexer on the pin where a fault is injected, the programmability of an FPGA enables us to add fault injection logic only to where fault injection function is desired. Hence, area overhead and performance impact can be significantly reduced.

A differential algorithm for concurrent simulation of path delay faults in sequential circuits is presented. The simulator analyzes all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output for vector pairs and considers the hazard states occurring between vectors. The main contribution is in methods of propagating signals between time frames. An optimistic method assumes that all nondestination flip-flops are not affected by delays. The pessimistic method converts all nondestination flip-flops with nonsteady values to the unknown state before these values are propagated beyond the time frame in which a path is activated. A 13-valued algebra is shown to improve the efficiency of fault simulation.

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible.

Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a circuit. Unlike stuck-at faults which can be detected using ATE at lower speed, test for path-delay faults require ATEs that can run at the clock frequency of the circuit under-test. However, with ever-increasing circuit-speed and complexity, ATEs are unable to keep up with this growing trend. Moreover running deterministic tests for timing related defects on expensive ATEs for high-speed circuits consume enormous test application time. In this paper, we propose a BIST methodology for path-delay faults in sequential circuits. The proposed technique is based on an existing BIST architecture for stuck-at faults such that timing faults in a circuit can also be addressed with minimum additional effort. A new clocking scheme along with a novel technique for placing observation points that increases the fault coverage for path-delay faults is presented. Experimental results on some benchmark circuits show high path-delay fault coverage for sequential circuits.

This paper outlines several problems related to the delay fault testing of sequential circuits. For timing test of a circuit and for layout optimization, critical path data are needed. When critical paths are identified by a static timing analyzer many of the selected paths cannot be activated functionally. Such paths are sequential false paths. However, many of these paths can be activated and tested in the full or partial scan mode due to the increased controllability and observability. Therefore, it is possible that detection of a timing error on a sequential false path, when scan mode is used, can lead to the rejection of a functionally good circuit. We propose that these paths should not be targeted during delay test if scan mode is used. Similarly, sequential false paths should not be used for layout optimization or for selection of maximum clock rate. We present a novel algorithm to identify these paths. This algorithm is based on functional analysis of each target path for single and multiple path activation. If a path cannot be activated either way, it is sequentially false.

We propose a delay test methodology for general sequential circuits. To test a combinational path between two flip-flops, the source flip-flop is initialized to the appropriate value, followed by creation of a transition, which is propagated through the path. An incorrect logic value is captured in the destination flip-flop if the path delay exceeds the clock period. The state of the destination flip-flop is observed at a primary output through path sensitization. Only one vector that propagates the transition through the path is applied with the rated clock period. All other vectors use a slow speed clock to ensure fault-free initialization and fault effect observation. The test generation method uses a 13-value algebra that represents the relevant transition and hazard states of signals. Since several path delay faults can be activated by the vector applied at the rated clock, only the flip-flops with hazard-free steady values are assumed to have deterministic states. This allows us to generate sequentially robust tests. We present the results of the test generation method on ISCAS benchmark circuits.

We propose a method of testing high-speed digital devices whose clock frequency exceeds the capability of the test equipment. The circuit is designed such that a controllable delay is introduced in the timing paths during test. With the added delay, the maximum operating frequency is lowered to a rate which is within the capability of the ATE. The delay circuit is so designed that its function is also testable. In an illustrative design with single clock, the controllable delay is incorporated within a master-slave flip-flop. The control of delay is then achieved by manipulation of the duty-cycle of the clock waveform. In a two-clock system, no modification of the flip-flop is required and the delay is varied by skewing one clock signal with respect to the other.

We examine the detectability of stuck-at faults when test vectors are applied at the rated speed. In the presence of path delays that are comparable to the clock interval, delayed signal transitions or timing hazards influence the detection of faults. It is, therefore, possible that a stuck-at fault that is detected by a test applied at slow speed, may not be detected with high speed test application. We present a fault simulation method that takes timing effects into account without specific delay modeling. Delay-hazard robust (dh-robust) coverage of a test sequence is defined as the coverage of single stuck-at faults that are guaranteed to be detected irrespective of delays or hazards. For tests generated for slow-speed testing, the dh-robust coverage can be quite low. However, special timing considerations in test generation provide better quality tests, especially for high performance circuits.

We show that a given initialization sequence for a synchronous sequential circuit is not guaranteed to work correctly when arbitrary path delays are present in the circuit. In this paper, we present a novel robust-initialization procedure for sequential circuits. This procedure guarantees the correct initialization of state elements of a sequential circuit regardless of delays in the circuit. Every pattern of the normal initialization sequence is repeatedly clocked in flip-flops, so that excessive delays on combinational paths feeding flip-flops do not prevent the proper initialization. This method guarantees the correct initialization of pipeline circuits. For a general sequential circuit which may have feedbacks, we give a simulation procedure to determine the initial state of the circuit that is guaranteed to be correct for arbitrarily large but bounded delays.>

We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified into three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modifying or resynthesizing the combinational logic as has been discussed by others. We find that almost 80% of sequentially untested faults are in category B. Most are not activated because the two successive states necessary to create a transition and to propagate it through the path cannot be produced in the sequential circuit. We study the partial scan technique in which flipflops are scanned to break cycles and show that a substantial increase in the coverage of path delay faults is possible.

Gives methods of test generation for partial scan circuits in which a single system clock controls all flip-flops in both functional and scan modes. Scan flip-flops are selected to break cycles. In comparison to circuits with separate scan clock, the single clock tests can cover most detectable faults with shorter test sequence. However, test generation time is increased.>

A mechanism is presented to represent failures in complex combinational digital and VLSI designs at a high level, referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed are based on the failure modes of the language constructs of a generic hardware-description language. Evaluation of such fault models is also reported through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.>