A realtime software MPEG transcoder has been developed. Novel motion vector reuse and SIMD optimization techniques are introduced to accelerate the transcoder without any quality degradation. Mean absolute error approximation criteria are employed in the reuse technique to refine scaled motion vectors. The developed transcoder on a Pentium II 266 MHz machine runs 2.5 times as fast as realtime, when scaling an MPEG-1 bitstream to half size.

This paper proposes an efficient memory mapping and a frame memory compression for an HDTV decoder LSI using Direct Rambus/sup TM/ DRAM (DRDRAM). The DRDRAM is employed to achieve the high memory bandwidth required for HDTV decoding at the minimum memory cost. The proposed memory mapping achieves a high memory bandwidth sufficient for HDTV decoding even in the worst case and no costly line buffers are required in the LSI for format conversion. The frame memory compression method reduces the memory cost by half and achieves HDTV decoding with a single 64 Mb DRDRAM chip without loss of memory access efficiency. Simulation results show that SNR degradation is 0.1 to 2 dB in the worst frame and no visible degradation is perceived except for a resolution chart sequence.

This paper proposes a frame memory compression method for an MPEG-2 Main Profile@High-Level (MP@HL) decoder LSI using Direct RambusTMDRAM (DRDRAM). The compression method is based on two-dimensional adaptive DPCM (2-D ADPCM) and is designed to achieve efficient memory access. HDTV bitstreams are decoded with a single 64 megabit (Mb) DRDRAM without subjective image quality degradation. Computer simulation is performed for ten HDTV bitstreams encoded at 22 Mbps. Simulation results show that, in the worst case, SNR loss compared to the full spec decoder is 0.71 dB for a luminance, 0.27 dB and 0.57 dB for chrominances.

This paper describes theoretical background of a mean absolute error (MAE) approximation method which was adopted as a half-pel motion estimation method in our real-time MPEG-2 codec VisuaLink 7000. We also propose an improved MAE approximation method which employs the horizontal and the vertical differentials of a source picture in addition to the MAEs of adjacent full-pel motion vectors. In general, any approximation method for MAE involves some loss of coding efficiency. However, the proposed method reduces loss of coding efficiency to 1/2/spl sim/3/4 of other existing methods with negligible increases of necessary computations and data transfers.

We propose a simplified motion estimation method which provides motion vectors for all types of motion compensation used in MPEG-2. The method is a result of applying a newly introduced approximation to the canonical three-step method described in the MPEG-2 Test Model. It reduces the number of necessary computations in the second and the third steps to less than 1%, and that of data transfers to about 8% of the canonical method. Total complexity of the proposed method is nearly that of the full-pel search motion estimation.

A programmable real-time high-definition television (HDTV) signal processor (HD-VSP) has been developed. For conventional TV signals, a previously reported video signal processor (VSP) has introduced flexible software control capability based on subregional processing. In order to expand such flexibility for real-time HDTV signal processing, the HD-VSP employs eight VSP clusters and programmable time-expansion/compression units. An input HDTV signal is converted to eight time-expanded subregional signals to reduce their sampling rate to that of conventional TV signals. The converted signals are then processed by the eight clusters in the same manner as the VSP. Therefore, programs developed for conventional TV signals can be applied to HDTV with little modification. Processed signals obtained from the eight clusters are time-compressed and multiplexed to reconstruct an output HDTV signal. This HD-VSP has 16 component processors per cluster and is capable of 2.5 giga-operations/s. Several coder programs, including a discrete cosine transform coder and an intraframe differential pulse code modulation (PCM) coder, are developed to evaluate HDTV coding efficiency.>

The architecture is an expanded version of a previously reported video signal processor in which a number of parallel processor clusters can be combined in a tandem connection form or in a parallel connection form. The new video signal processor introduces programmable time-expansion and time-compression circuits to A-to-D and D-to-A converters, respectively, for coping with high speed HDTV signals. It also employs input/output switch units before and after parallel processor clusters. The introduction of input/output switch units to the parallel processor clusters makes it possible to input several video signals simultaneously. By these additional units, a HDTV signal is converted to a set of NTSC level video signals in the time-expansion circuit. Every NTSC level video signal is then delivered to parallel processor clusters through an input switch unit. After processing in clusters, NTSC level signals are converted to a HDTV signal through an output switch unit and time-compression circuits. This architecture can be applied to stereo scope processing. >

To increase efficiency on interframe coding and/or to preserve speaker privacy for videophone applications, a method for real-time background separation based on stereoscopic range finding is developed. The algorithm includes foreground center extraction, foreground threshold calculation, occlusion-free direct block matching with quadtree block subdivision, and contour segmentation using a motion edge. The algorithm is evaluated using a stereo-video sequence. For an application using the background separation technique, background filtering is introduced. Background filtering can decrease the number of inessential coded blocks, when applied to a motion-compensated hybrid differential pulse-code modulation (DPCM)/transform coder. If the cut-off frequency for filtering characteristics is further lowered, the filtering will conceal details in the background.>

A single-board 14.3-MOPS (million operations per second) video signal processor module (VSPM) has been developed. The module is fully microprogrammable and processes up to a 128 pel*128 pel subimage every 16.7 ms. Using a number of homogeneous VSPMs aligned in parallel, a real-time video signal processing environment is provided on the basis of an overlap-save or overlap-add technique. An experimental system has been constructed in order to demonstrate the signal processor approach's effectiveness for video signals by implementing picture coding algorithms. Due to software control capability, various kinds of picture coding techniques can be evaluated by the system.>

Two important functional LSIs for the realtime Video Signal Processor (VSP) have been developed. One is the Pipelined Arithmetic Unit (PAU) and the other is the Address Generation Unit (AGU). The PAU chip employs a flexible pipelined architecture optimized for L1 or L2-norm distance calculation, used in a wide variety of image processing. The AGU chip, including 15-word register file for pointer alteration, offers a user-friendly two dimensional pointer addressing. A realtime Video Signal Processor Module (VSPM), composed of one PAU, four AGUs and memories, has been implemented for multiprocessor VSP configuration. Thanks to software control capability, various kinds of picture coding techniques can be evaluated by the system.

A real-time video signal processor (VSP), suitable for VLSI implementation, is proposed. In order to obtain software controllability for video signal processing in a real-time environment, the VSP employs a multiprocessor configuration, where a plural number of video signal processing modules (VSPMs) are connected to input, output and feedback buses. Each VSPM processes its own assigned sub-images without communicating from/to other VSPMs. As the VSP needs no overhead for VSPM communication, the number of VSPMs involved does not affect the VSP system performance. The homogeneous processor based approach, employed in VSP, will become the most suitable LSI implementation methodology in the near future, due to processor module regularity and system flexibility.