We present a technique for identifying redundant crosspoint faults in, sequential PLAs with fault-free hardware reset. This technique can find most redundant crosspoint faults efficiently. Experimental results show that about 7% of crosspoint faults are redundant on an average in the sequential PLAs synthesized by a commercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks.

We have specified typical fabrication defects of the rapid single-flux-quantum (RSFQ) based logic gates, and then investigated the behavior of defective gates by SPICE simulation to estimate the defect coverage of logic testing. The simulation results show that the logic testing based on the stuck-at fault model can achieve at most 65% defect coverage for pulse-driven dual-rail RSFQ logic circuits and the defect coverage may increase up to 80% by properly adding two-pattern tests to the stuck-at fault tests.

We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS'89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable.

This paper discusses limitations of logic testing and capabilities of current testing for logic circuits consisting of the current injection logic gates with four Josephson junctions (4JL gates). We have specified typical fabrication defects of the 4JL gates, and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that almost half defects cannot be detected by logic testing while more than 90% defect coverage is achievable by monitoring power supply current under multiple test vectors. We have also proposed a current testing scheme for Josephson combinational circuits.

This paper presents a simple technique for locating single gate-level faults in combinational circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to evaluate its performance. The computation time is very short while a high diagnostic resolution may not always be guaranteed. Therefore this would be useful as a preprocess for analyzing the physical defect by various tools such as scanning electron microscopy, electron beam probing and light emission microscopy.

A PLA design system called PLAYER has been developed for next generation VLSI products. It supports the top-down design of PLAs from a functional description to a mask level layout with easy-testable features for built-in test. Highly effective optimization and verification tools are provided to realize correct and area-efficient designs.

Undetectable bridging faults between two arbitrary leads, which may produce feedback loops, in a unate two-level irredundant AND-OR network are anlyzed and their effect on stuck-at fault detection tests is explored. As a result, any complete test set for single stuck-at faults proves to still remain valid in the presence of undetectable bridging faults.

Theorem 2ii), Theorem 7, and Corollary 5ii) with respect to detection and location of feedback bridging faults in the above paper1 are shown to be incorrect by counterexamples. In addition, some misunderstandings about asynchronous behavior of a faulty network with a feedback bridging are pointed out.