The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this paper, for the first time, utilizes this information to find an optimal retiming. The clock period is guaranteed to be at most one gate delay larger than the optimal clock period found using skew alone; note that since skew is a continuous optimization, it is possible that the optimal period may not be achievable. The method views the circuit hierarchically, first solving the clock skew problem at one level above the gate level, and then using local transformations at the gate level to perform retiming for the optimal clock period. The solution is thus divided into two phases. In Phase A, the clock skew optimization problem is solved with the objective of minimizing the clock period, while ensuring that the difference between the maximum and the minimum skew is minimized. Next, in Phase B, retiming is employed and some flip-flops are relocated across gates in an attempt to set the values of all skews to be as close to zero as possible.

The introduction of clock s k ew at an edge-triggered ipop has an eect that is similar to the movement of the ip-op across combinational logic module boundaries, and these are continuous and discrete optimizations with the same eect.While this fact has been recognized before, this work, for the rst time, utilizes this information to nd a minimum/speci ed period retiming eciently.The clock period is guaranteed to be at most one gate delay larger than a tight l o w er bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming.All ISCAS89 circuits can be retimed in a few minutes by this algorithm.1 \astra" ( ): (Sanskrit) a sophisticated weapon.

This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clock skews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In a paper by J.P. Fishburn (see IEEE Trans. on Computers, vol. 39, no. 7, p. 945-951, 1990) the problem of clock period optimization is formulated as a linear program. We first propose an efficient graph-based solution that takes advantage of the structure of the problem. We also show that the results obtained by Fishburn may result in exceedingly large skews, and propose a method to reduce these skews without sacrificing the optimality of the clock period. Experimental results on several ISCAS89 benchmark circuits are provided.>