A switchbox router utilizing layers is presented. Each net is first partitioned into a set of subnets. This decomposition is driven by the minimum Steiner tree. The construction is then carried out on a step-by-step basis, which allows the system to dynamically take new information on the problem into account. The information is examined by a set of expert systems which decide which subnet should be routed next. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. The program has been implemented in the LISP programming language. Many test cases have been run successfully, and some results, including Burstein's difficult switchbox, are presented.>

A two-dimensional router utilizing two layers is presented. The routing technique can be described as follows: After partitioning of the nets into a set of subnets, the construction is carried out on a step-by-step basis, which allows the system to dynamically take into account new information. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. To provide a solution to a given problem, the router expands the switch-box by adding rows dynamically where they are needed. Many test cases have been run successfully, and some results, including Burstein's difficult switch-box, are presented.>

This paper describes one of the new methodologies for IC design currently being used at the CNET. The main features detailed are the symbolic layout method called MDMOS and the integrated CAD system CASSIOPEE. Its most significant advantages are design safety, elimination of costly and inefficient checks and supply of technical specifications which are always up-to-date. This methodology is described in its entirety starting from the logical description, and including all stages up to masks generation.