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Dorin Patru

dblp:47/6415 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2023
0009-0008-5671-9061ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% High-performance computing · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache management
0.712023
Cache Programming for Scientific Loops Using Leases · ACM Trans. Archit. Code Optim. 2023
Memory systems › memory access optimization
data movement reduction
0.712023
Cache Programming for Scientific Loops Using Leases · ACM Trans. Archit. Code Optim. 2023
High-performance computing
scientific computing
0.212023
Cache Programming for Scientific Loops Using Leases · ACM Trans. Archit. Code Optim. 2023

Methods — techniques the papers use, named apart from their topics

lease programming · 0.7FPGA emulation · 0.7
YearPublicationVenuePosition
2023 Cache Programming for Scientific Loops Using Leases
abstract
Cache management is important in exploiting locality and reducing data movement. This article studies a new type of programmable cache called the lease cache. By assigning leases, software exerts the primary control on when and how long data stays in the cache. Previous work has shown an optimal solution for an ideal lease cache. This article develops and evaluates a set of practical solutions for a physical lease cache emulated in FPGA with the full suite of PolyBench benchmarks. Compared to automatic caching, lease programming can further reduce data movement by 10% to over 60% when the data size is 16 times to 3,000 times the cache size, and the techniques in this article realize over 80% of this potential. Moreover, lease programming can reduce data movement by another 0.8% to 20% after polyhedral locality optimization.
Benjamin Reber, Matthew Gould, Alexander H. Kneipp, Fangzhou Liu 0004, Ian Prechtl, Chen Ding 0001, Dorin Patru
ACM Trans. Archit. Code Optim.8
2022 Cache-coherent CLAM (WIP)
abstract
Traditional caches are automatic and cannot be controlled directly by software. A recent design called CLAM manages a cache using leases and lets a program specify these leases. The lease cache is mostly controlled by software. This paper extends CLAM to support multiple cores with private caches. It presents the hardware extensions to support cache coherence for data-race free (DRF) programs. CLAM can use either inclusive or exclusive caching for shared data. Its performance can be improved by two programming techniques: cache draining and reference privatization.
Chen Ding 0001, Benjamin Reber, Dorin Patru
LCTES3
1999 Detection and Identification Communication Protocols for Wireless Biodevice Networks
abstract
This paper presents the definition and analysis of three detection and identification protocols for a future wireless biodevice network (WBDN). These protocols represent the first part of a complete communication protocol for a WBDN. The number of detected and identified biodevices depends only on the time the user accepts to assign for the detection and identification phase of a communication session.
Kent L. Jones, Mark L. Manwaring, Dorin Patru
CBMS3