The verification of power grids in modern integrated circuits must start early in the design process when adjustments can be most easily incorporated. This work describes a vectorless verification technique that deals with circuit uncertainty in the framework of current constraints. In such a framework, grid verification becomes a question of computing the worst-case voltage drops which, in turn, entails the solution of as many linear programs (LPs) as there are nodes. First, we extend grid verification to also check for the worst-case branch currents. We show that this would require as many LPs as there are branches. Second, we propose a starkly different approach to reduce the number of LPs in the verification problem. We achieve this by examining dominance relations among node voltage drops and among branch currents. This allows us to replace a group of LPs by one conservative and tight LP. Results show a dramatic reduction in the number of LPs thus making vectorless grid verification in the framework of current constraints practical and scalable.

As part of early system design, one must verify that the power grid provides the underlying logic circuitry with voltage levels that are within specified ranges. In this paper, we describe a vectorless verification approach that can be applied early in the design process. We adopt an RLC model of the grid in the framework of current constraints that capture uncertainty about circuit details and activity. With just a few linear programs and one linear system solve, our proposed approach provides tight conservative bounds on the maximum and minimum worst-case voltage drops at every node of the grid. Results show the accuracy and speed of our technique thus making it practical and scalable.

Power grid verification in modern integrated circuits is an integral part of early system design where adjustments can be most easily incorporated. In this work, we describe an early verification approach under the framework of current constraints where worst-case node voltage drops are computed via linear programs proportional to the grid size. We propose an efficient method based on a sparse approximate inverse technique to greatly reduce the size of such linear programs while ensuring a user-specified over-estimation margin (in volts) on the exact solution.

As part of integrated circuit design verification, one should check if the voltage drop on the power grid exceeds some critical threshold. One way to do this is by simulation, but that is computationally expensive and gets prohibitive for large circuits with a large variety of possible operational modes. Another limitation of a simulation-based approach is that it requires complete knowledge of the logic circuitry drawing current from the grid, thus precluding grid verification early in the design process. In this paper, we model the grid as an RLC circuit and we propose three verification techniques that can be applied in the early stages of the design process. These techniques do not require exact knowledge of the circuit currents. Instead, the currents drawn by the logic beneath the power grid are described by means of current constraints that capture the uncertainty about circuit details and activity. The first verification approach gives the exact worst-case voltage drop at every node of the grid, but it is slow. A second faster approach gives conservative bounds on the worst-case voltage drop at every node of the grid. The third approach is much faster; it is a conservative approach which simply checks if the grid voltage drop exceeds some pre-defined thresholds, without actually computing the worst-case voltage drop at every node.