Layout hotpot detection is one of the main steps in modern very-large-scale-integration (VLSI) chip design. A typical hotspot detection flow is extremely time consuming due to the computationally expensive mask optimization and lithographic simulation. Recent researches try to facilitate the procedure with a reduced flow, including feature extraction, training set generation, and hotspot detection, where feature extraction methods and hotspot detection engines are deeply studied. However, the performance of hotspot detectors relies highly on the quality of reference layout libraries which are costly to obtain and usually predetermined or randomly sampled in previous works. In this article, we propose an active learning-based layout pattern sampling and hotspot detection flow, which simultaneously optimizes the machine-learning model and the training set that aims to achieve similar or better hotspot detection performance with much smaller number of training instances. Experimental results show that our proposed method can significantly reduce lithography simulation overhead while attaining satisfactory detection accuracy on designs under both DUV and EUV lithography technologies.

Although many physical limitations have been reached in modern micro-lithography, printed critical dimensions continue to shrink according to the International Technology Roadmap for Semiconductors (ITRS) [1]. To meet the demands imposed by this guideline, the traditional separation between design and manufacturing communities is being bridged. Many EDA tools package manufacturing data for delivery into established simulation engines for design verification. However, none of them provide practical implementations of design optimizations at an early stage in the design flow.This paper presents an automated layout modification flow for metal layers with the goal of enhancing manufacturability. It can easily be deployed in a current custom design flow in a way that is visible to designers. The result of this scheme is improvements to process windows and yield, while minimizing circuit performance detractors. The flow is verified through analyses of both the impact on circuit performance and the benefit to manufacturability. It has been implemented in a state-of-the-art 65 nm chip design. Both silicon yield and electrical performance data are currently being collected and analyzed.