Demo Data from EDBT 2026 / reviewers in the wild / expert
Vinay C. Patil
dblp:47/9980
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2019
0000-0001-9076-2727ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Security and privacy · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Electronic design automation · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
hardware obfuscation |
0.3 | 1 | 2017 | Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques · IEEE Trans. Inf. Forensics Secur. 2017 |
Hardware security and side channels › hardware obfuscation
logic obfuscation |
0.3 | 1 | 2017 | Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques · IEEE Trans. Inf. Forensics Secur. 2017 |
Electronic design automation › hardware security
design for security |
0.1 | 1 | 2017 | Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques · IEEE Trans. Inf. Forensics Secur. 2017 |
Integrated circuit design
VLSI design |
0.1 | 1 | 2017 | Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques · IEEE Trans. Inf. Forensics Secur. 2017 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Efficient Testing of Physically Unclonable Functions for UniquenessabstractPhysically unclonable functions (PUFs) have emerged as lightweight hardware security primitives for implementing secure authentication. Strong PUFs rely on random manufacturing process variation to create unique Boolean mappings from input (challenge) to output (output). For secure authentication, challenge to response mappings are required to be unique for each device. However, uniqueness is not guaranteed by design or manufacturing. Testing for uniqueness and weeding out non-unique parts are the only way to ensure uniqueness of devices. Uniqueness testing can be expensive in time as the challenge-responses of the N th device under-test, must be proven to be different from previously tested N - 1 devices, or the device must be discarded. To reduce the time complexity of uniqueness testing, Multi-Index hashing (MIH) was proposed for online testing in high volume manufacturing. Database search using MIH was shown to be fast, but it suffers from high memory cost. In this paper, we address the memory problem of MIH based uniqueness testing by proposing alternative MIH strategies. Our results indicate that the proposed search strategies can significantly reduce the memory cost without sacrificing performance, requiring ≈ 3.35× less memory with just a 17% performance overhead when testing the uniqueness of 1 million PUFs. Leandro Santiago de Araújo, Vinay C. Patil, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu |
ATS | 2 |
| 2017 | A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUFabstractSRAM-based Weak PUFs have become popular in tamper sensitive key storage and device ID generation. Weak PUFs rely on intrinsic process variations to produce repeatable and unique start-up behavior. However, noise in the system compromises repeatability of SRAM start-up behavior. To obviate this problem, a number of solutions such as fuzzy extraction and error correcting codes have been proposed to generate a stable key from error-prone PUF cells. Unfortunately, the overhead from these techniques grows superlinearly with increasing error rate. Recently, it was suggested that the start-up error rate can be reduced significantly by accelerating device aging, which leads to reduced overhead for error correction. To accelerate aging, devices are subjected to temperature and voltage stress in a burn-in chamber. Unfortunately, burn-in accrues significant production cost. In this paper, we present a method to reduce the cumulative burn-in time by quantifying the minimum burn-in requirement for each device. We propose a low-cost proxy to measure the degree of process variation of each device at birth and use previously proposed device aging model to determine the burn-in requirements. Our results show that this procedure reduces cumulative burn-in cost without compromising the resultant reliability of Weak PUFs. Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu |
ISCAS | 2 |
| 2017 | Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level TechniquesabstractThe threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions. Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu |
IEEE Trans. Inf. Forensics Secur. | 2 |