This paper proposes a unified bidirectional power electronics converter having reconfigurable features for both electric vehicle (EV) onboard charging (OBC) and propulsion. In addition, it also has the feature of vehicle-to-grid (V2G) operation for efficient power management. This converter is suitable for bidirectional operation, which enables it to operate as an AC-DC converter for battery charging and DC-AC converter for propulsion operation. During forward operation, it uses a single stage to replace two conventional onboard charging stages. Similarly, during propulsion, it reduces two stages by using a single stage of DC-AC operation. The reconfiguration of the converter for different modes is done by relay switches to reduce the control complexity of the semiconductor switches. Repurposing two of the three machine windings as boost inductors in the interleaved totem pole power factor correction (PFC) stage during charging reduces the count of passive components and system cost. The input is a single-phase AC voltage of 230V, 50Hz to charge the 400V battery, which is used to drive a three-phase permanent magnet synchronous machine (PMSM) in propulsion mode. This helps reduce system size by integrating the converter in a single stage with the switching frequency of 100kHz. High efficiency is achieved with the inherent property of zero voltage switching (ZVS). The complete analysis and simulation of the proposed system are included in the paper. A 3.6kW laboratory prototype is built for hardware demonstration.

The popularity of electric vehicles (EVs) is increasing day by day to reduce the carbon footprint and to protect the environment. The batteries are the main source of power for the EVs. Among all the available batteries, the Li-ion batteries are very popular in EV applications. These batteries are sensitive to temperature variation and suffer significant performance degradation at sub-zero temperatures. This problem not only impacts system reliability but also affects EV performance by reducing the driving range. To overcome this problem, it is important to maintain battery temperature within a suitable range of 15°C to 35°C for stable operation. Hence, this paper proposes an integrated resonant circuit for battery temperature modulation. This unique circuit is designed to operate in both battery temperature modulation and power transfer mode. In the temperature modulation mode, it can circulate the current through the batteries to increase the battery temperature. During the power transfer mode, the battery supplies power to the EV motor for driving purposes. This converter has another unique feature of utilizing motor inductance as part of the resonant network during heating operation. In this way, the system operates without an external power source and leverages integrated resonant tank components to generate alternating current heating. This paper presents the design, working modes, experimental implementation, and performance analysis of the proposed circuit. The hardware result shows the effectiveness of internal heating. This paper includes a temperature rise from 8. 6°C to 25.4°C in a short duration of 274sec with the rise rate of 0. 061°C/ sec. The proposed system reduces the converter's size and cost.

The battery capacity is one of the major issues to achieve long range and getting acceptance of electric vehicles (EVs) over conventional vehicles. Another major issue is related to required charging time in EVs compared to conventional vehicles. These problems can be solved by implementing fast charging station, which needs high power charging facility. Additionally, battery swapping facility can reduce the charging time further. Hence, the swappable battery station based on fast charging algorithm is desirable for EVs transformation. In this paper, a novel algorithm for fast battery swappable charging station is proposed in order to reduce initial purchase price, minimize charging time and increase driving range. The proposed swappable battery charging station is powered from both the grid and solar PV supplies to supply high power during fast charging. This algorithm allows charging of the swappable as well as fixed batteries within half an hour. The analysis and simulation of the proposed control technique and converter configurations is included. The experiment is performed in the laboratory to validate the proposed fast charging algorithm for both the swappable and fixed batteries in a DC microgrid environment.

Automated charging for driverless electric vehicles is necessary for fast adoption in electric transportation systems. The wireless charging systems can provide automated charging solution. This paper presents a DC-DC converter for magnetically coupled wireless power transfer (WPT) charging. The converter offers significant advantage by regulating a wide output voltage range for the WPT system, facilitating both constant voltage and constant current modes of battery charging to improve the battery life. Additionally, the proposed converter achieves zero voltage switching of all switches operating in a high frequency across the wide output voltage range. The paper provides a detailed analysis and design methodology of the circuit. Finally, a 900W experimental prototype WPT system is developed to demonstrate the power transfer over a 100mm air gap.

Nowadays, energy storage plays a crucial role in electric vehicles. The existing constant current constant voltage charging methods can accelerate damage inside the battery by causing a loss of lithium ions, if a high current (more than 1C) is injected. Hence, a new optimized charging algorithm is proposed in this paper. In this charging method, four charging algorithms are combined, which are pulse current charging (0% to 20% SOC), pulse and burp current charging (20% to 80% SOC), and constant current constant voltage charging (above 80% SOC). This proposed hybrid charging algorithm reduces the charging time to less than an hour. One of the important features of this charging algorithm is that it charges the battery in pulse charging and pulse and burp charging modes at low frequency (2.5 Hz). Additionally, the negative current pulse in pulse and burp charging mode helps to mitigate the issue of lithium plating on the surface of the negative electrode during the charging process. Hence, the proposed method optimizes the performance of the battery to improve the battery life. The proposed algorithm is implemented in a bidirectional DC-DC power converter to verify the operation. The simulation and experimental results of the proposed charging method are included in this paper which shows, improvement of the battery life. The experimental results are also included in this paper.

The wide bandgap (WBG) semiconductor device-based converters offer improved performance over Si-based converters. In addition to increased efficiency the WBG-based power converters minimizes converter size due to capability of operating at high switching frequency. The GaN semiconductor device is having higher efficiency among all the existing semiconductor devices. To apply these devices in power converters the lifetime of the converters is important to analyze under application-specific condition. Hence, reliability analysis of the GaN-based dual active bridge converter is considered in this paper. The reliability analysis method of the GaN-based converters is required due to its unique structure and properties. Hence, a novel reliability analysis model is proposed in this paper to determine the lifetime of a GaN converter. This converter is used for an onboard charger application of electric vehicles (EVs). The lifetime is analyzed by considering the constant current and constant voltage charging method of EVs. The proposed model is verified in simulation and analysis considering a 2kW EV charger. Additionally, the experimentation is performed to validate the model. The preliminary results are included in this paper.

With increasing use of runtime polymorphism and reliance on runtime type interpretation, the presence and importance of indirect branches has seen a considerable rise in recent workloads. Evidently, accurate target prediction for indirect branches has emerged as an important problem. While direction prediction of direct branches has received considerable research attention leading to efficient prediction policies and hardware structures implemented inside modern processors, proposals for target prediction for indirect branches has been relatively few. The problem of accurate target prediction for indirect branches is significantly tough since these transfer control to an address stored in a register that is known only at runtime. Unlike conditional direct branches, indirect branches can have more than two targets to be resolved at runtime, for which prediction requires a full 32-bit/64-bit address to be predicted, in contrast to just a taken or not-taken decision as needed for direction prediction of direct branches. Recent research shows indirect branches, being mispredicted more frequently, can start to dominate the overall branch misprediction cost. In modern processors, the only hardware structure available to facilitate target address prediction for indirect branches is a fixed-size Branch Target Buffer (BTB). BTB is often designed as a set associative cache for storing recent target addresses for branch instructions encountered during execution, with a motivation of being able to reuse the same addresses for future instances, thereby saving latency cycles. Evidently, designing efficient indexing schemes and replacement mechanisms for BTB structures is crucial, more so, for indirect branches, since these serve as the only prediction handle. In this paper, our objective is to examine a hierarchical BTB design for multicores with total size comparable to what exists today, with a motivation towards possible improvement of prediction accuracy by facilitating collaborative constructive learning between programs executing in different cores that encounter similar histories. Specifically, we wish to propose the concept of a small on-chip L1 BTB inside each core, supported by a larger off-chip L2 BTB shared among the cores. Our motivation towards a hierarchical BTB design is twofold. On one hand, in a multiprogramming environment, where the same program is executed in multiple cores, on different test cases, there is a significant potential of target information reuse for indirect branches, as is evident from our experiments on SPEC 2006 workloads. This is typically useful for machine learning based workloads where the training phase is often executed in different cores with the same neural network being trained on different training sets. On the other hand, with different programs in different cores, there is some chance of reuse as well, due to sharing of system libraries. The essence of our idea rests on the fact that programs executed in different cores have similar history patterns that can similarly influence the target addresses. Our design aims to decrease on the on-chip L1 BTB size while investing more storage for the off-chip shared L2 BTB. Suitable allocation and replacement policies support our hierarchical design. Initial experiments show expected accuracy benefits.

Improving the dc voltage gain of power converters has been the primary focus of the current and past research in the area of power electronics. This work presents another solution to widen the range of the output voltage. It proposes three reconfigurable steps for the output voltage. The range of the output voltage varies up to four times the base level. These configurations together vary the output voltage from 15 to 96 volts. A soft switched dc-dc power converter is built with the traditional topology of phase shifted full bridge converter along with improved characteristics. For better management of the transformer loss, a configuration of four transformers has been employed. The proportional gate drive approach is implemented to obtain four similar isolated blocks of the output voltage. This makes it possible to either configure these blocks all in series, parallel or in series/ parallel combination of two. The concept is verified in a low-profile prototype. The hardware is characterized up to the load power of 1kW for the input voltage of 400Vdc. The converter reports better efficiency over the complete range of output voltage.

The high frequency capability and low on-state losses of Gallium Nitride (GaN) transistors offer the potential to increase converter efficiency and/or reduce heatsink and passive component size. This paper investigates the use of GaN technology to enhance the performance of power factor correction (PFC) and LLC converters for battery charging applications. First the efficiency performance of non-isolated PFC converters using GaN transistors is compared by simulation, the asymmetric bridgeless PFC converter is shown to achieve the best efficiency, with a predicted figure of 99% in a 1MHz, 200W design. The predictions are validated by an experimental prototype using a GS66502B, GaN Systems E-mode GaN transistor. Then the efficiency comparison of the PFC and LLC converter using GaN devices for battery charging applications is included in the paper. The experimental results of the PFC converter with GaN devices are also included. Additionally, this paper includes the analysis and design of a common mode input filter for the GaN-based high frequency converters for battery charging application. The size of both the converters using GaN devices is reduced by 40% than the converters based on Si devices. The switching loss comparison of GaN and Si devices are also included in the paper.

Speculative execution is an optimization technique used in modern processors by which predicted instructions are executed in advance with an objective of overlapping the latencies of slow operations. Branch prediction and load value speculation are examples of speculative execution used in modern pipelined processors to avoid execution stalls. However, speculative executions incur a performance penalty as an execution rollback when there is a misprediction. In this work, we propose to aid speculative execution with approximate computing by relaxing the execution rollback penalty associated with a misprediction. We propose a sensitivity analysis method for data and branches in a program to identify the data load and branch instructions that can be executed without any rollback in the pipeline and yet can ensure a certain user-specified quality of service of the application with a probabilistic reliability. Our analysis is based on statistical methods, particularly hypothesis testing and Bayesian analysis. We perform an architectural simulation of our proposed approximate execution and report the benefits in terms of CPU cycles and energy utilization on selected applications from the AxBench, ACCEPT, and Parsec 3.0 benchmarks suite.

In recent times, approximate computing is being looked at as a viable alternative for reducing the energy consumption of programs, while marginally compromising on the correctness of their computation. The idea behind approximate computing is to introduce approximations at various levels of the execution stack, with an attempt to realize the resource hungry computations on low resource consuming approximate hardware blocks. However approximate computing for program transformation faces a serious challenge of automatically identifying core program areas/statements where approximations can be introduced, with a quantifiable measure of the resulting program correctness compromise. Introducing approximations randomly can cause performance deterioration without much energy advantage, which is undesirable. In this paper, we introduce a verification-guided method to automatically identify program blocks which lend themselves to easy approximations, while not compromising significantly on program correctness. Our method is based on identifying regions of code which are less influential for the computation of the program outputs and therefore, can be compromised with, however still having a potential of significant resource reduction. We take the help of assertions to quantify the effect of the resulting transformations on program outputs. We show experimental results to support our proposal.

Software evolution has been extensively studied in the past decade for various properties and interesting patterns. In this work, we study the effect of evolution on branch prediction techniques. Typically for any program, at the hardware level, all dynamic branch prediction strategies learn the branch behaviors at run time and later re-use them to predict the direction of future branches. The duration of the learning curve depends heavily on the kind of technique used and also the complexity of the program at hand. We propose that saving the branch outcome profile from an older version and reusing it in a new version can significantly reduce this overhead and improve performance. In this paper, we discuss the effect of program evolution on the performance of branch prediction, study how the individual branches get affected during evolution, suggest a new method to reuse the branch behavior information from a previous version, and share our results on various software repositories. Preliminary results indicate our intuitions are well justified.

Several solar PV systems require a high gain front end dc-dc converter. Conventional dc-dc converters can offer limited gain and their efficiency drops as the gain requirement increases. This paper proposes a high gain, high efficiency dc-dc converter suitable for low voltage PV fed applications. The underlying concept of the converter is based on energy storage in an intermediate capacitor by a coupled inductor. In the proposed converter, a clamp circuit is used to recycle the energy stored in the leakage inductance (of the coupled inductor) to increase the efficiency. This facilitates realization of high voltage gain without extreme duty cycle. Presence of a clamp circuit reduces voltage stresses in the main switch, which leads to the use of low voltage switch having a low “on-state” resistance (RDS(ON)). Also, diode reverse recovery problem is eliminated, which reduces the losses across the diode and improves the efficiency. The operational principle of the converter is discussed in detail and all the relevant analysis is included.