Demo Data from EDBT 2026 / reviewers in the wild / expert
James R. Anderson 0001
dblp:48/107
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 47% Reconfigurable computing and FPGAs · 18% Hardware accelerators and domain-specific architectures · 18% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › network performance analysis
network performance modeling |
0.0 | 1 | 2000 | Performance-Based Constraints for Multidimensional Networks · IEEE Trans. Parallel Distributed Syst. 2000 |
Performance modeling and evaluation
queueing models |
0.0 | 1 | 2000 | Performance-Based Constraints for Multidimensional Networks · IEEE Trans. Parallel Distributed Syst. 2000 |
Integrated circuit design › digital signal processing circuits
finite impulse response filter |
0.0 | 1 | 1998 | A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering · FPGA 1998 |
Hardware accelerators and domain-specific architectures
signal processing accelerator |
0.0 | 1 | 1998 | A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering · FPGA 1998 |
Methods — techniques the papers use, named apart from their topics
stochastic analysis · 0.0simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Performance-Based Constraints for Multidimensional NetworksabstractA stochastic analysis of multidimensional networks with unidirectional or bidirectional links between nodes is presented. The analysis allows the development of an accurate model for examining the performance and cost trade-offs of different network configurations. The model is validated through simulation and does not rely on the simplifying assumptions of previous models. In addition, the model is valid for the hypercube network. Two new performance-based design constraints are introduced: constant maximum throughput and constant unity queue. These new constraints are fundamentally different than previous constraints, which are based on some characterization of hardware implementation costs. Both of the new constraints allow performance and cost comparisons of different network configurations to be made on the basis of an equal ability to handle a range of traffic load. Results under the new constraints clearly show that a low dimensional network, while offering the lowest message latency, must be significantly more expensive than a comparable high dimensional network and, in some cases, may be impractical to implement. In addition, the constraints demonstrate that performance is highly dependent on offered load. James R. Anderson 0001, Seth Abraham |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 1998 | A Coarse-Grained FPGA Architecture for High-Performance FIR FilteringabstractThis paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar to that of a custom ASIC design, while allowing all of the basic FIR design parameters, including coefficient precision, to be configured. Previous research has already shown that FPGAs can provide a high-performance alternative to DSP processors. Experimental comparisons in this paper show that the performance and area efficiency of the proposed architecture is similar to that of custom approaches across a wide range of filter sizes and configurations. James R. Anderson 0001, Siddharth Sheth, Kaushik Roy 0001 |
FPGA | 1 |
| 1997 | Multidimensional Network Performance with Unidirectional LinksabstractA stochastic analysis of multidimensional networks with unidirectional links between nodes is presented, which is more accurate than previous models and valid for the hypercube. The results are reconciled with those of previous researchers who have reported conflicting conclusions. In addition to the classic constraints of constant link width, pin-out, and bisection width, a new constraint, constant maximum throughput, is introduced. This constraint dramatizes the performance and cost trade-offs between different network topologies. James R. Anderson 0001, Seth Abraham |
ICPP | 1 |