While optimizing for core hardware performancerelated target metrics, frameworks for approximate accelerators often overlook the reliability aspect. Approximated implementations obtained by these frameworks can potentially differ in terms of reliability and may impact the reliability of the overall system. In particular, approximation changes the data profiles transmitted between system modules, which can trigger crosstalk on interconnect lines and aggravate electromigration. We propose a two-stage process that performs a reliability assessment of the circuit interconnects after the approximate accelerator synthesis. Our approach aims to find the most reliable solutions from the approximate candidate circuits generated by an automated approximation flow. We then leverage Pareto-filtering to strike a balance between area, reliability, and accuracy. Notably, the selected designs achieve up to a 178% improvement in mission time compared to the original accelerator, and a 68% improvement over designs optimized solely for area. In addition, our methodology allows custom priority settings to be adaptable to a user's preference, thereby leading to circuits that meet diverse design constraints. Our experimental results show the effectiveness of our methodology in achieving superior trade-offs between area, reliability, and accuracy, hence uncovering a new dimension for approximate accelerator design methodologies.

Many applications allow errors during communication as long as their sizes or rates are limited. These applications are perfect candidates for approximate communication and provide sufficient degrees of freedom to optimize the communicated data for performance, power, reliability and safety within certain error bounds. In this study, we present a novel approach for approximate communication which is specifically tailored to the streaming of data between sensors and control units on narrow parallel buses. To meet the performance goals, the presented approach relies on base-delta compression, where a base value is followed by a sequence of differences to it (deltas). To ensure an efficient low power transmission of data as well as a high reliability and safety at the same time, the approach uses a Gray code for bus encoding and approximates the data within given error bounds, such that crosstalk induced faults and currents are minimized and the overall switching activity is kept low.

Interconnect is essential for the performance, power consumption, and safety of modern digital circuits. In the context of approximate computing, various methods have been proposed to improve the system performance by decreasing the amount of transmitted data or reducing power consumption through reduced switching activity on the interconnects. However, their impact on the reliability and safety of interconnect has not yet been evaluated. In this work, the effects of approximate communication on the reliability and safety of interconnects in digital circuits are assessed. The results show that while these methods increase performance, they can also harm the reliability and mission time of interconnects. We propose some modifications to address the safety and reliability issues when using approximate communication. Our results show that these modifications can increase the mission time, and establish a proper balance between performance, power consumption, and safety.

Abstract Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induced variations lead to different sizes of crosstalk defects. The largest crosstalk defects are detected by conventional interconnect test methods, while the smaller ones do not change the system behavior and are left without detection. In this paper, we show that even smaller crosstalk defects have an inevitable impact on electro-migration (EM) degradation. They increase the current that conveys through the wire and consequently result in more EM degradation and shorter mean time to failure of the system. Simulation results show that in the worst case the EM degradation increases up to 90%, however, even in the normal situation 7.2% degradation can be observed for the PARSEC 2000 benchmark Because these Hidden Interconnect Defects cause different small delay sizes, we propose a multi-frequency test method to detect them properly. Our experimental results for 8000 different 32-bit interconnect layouts show that, on average, 6 frequencies and 81 test patterns are required for finding hidden interconnect defects.

STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.

Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to severalprocessors and ITC benchmarks and have looked at its effectiveness for these circuits.

By increasing the complexity of digital systems, verification and debugging of such systems have become a major problem and economic issue. Although many computer aided design (CAD) solutions have been suggested to enhance efficiency of existing debugging approaches, they are still suffering from lack of providing a small set of potential error locations and also automatic correction mechanisms. On the other hand, the ever-growing usage of digital signal processing (DSP), computer graphics and embedded systems applications that can be modeled as polynomial computations in their datapath designs, necessitate an effective method to deal with their verification, debugging and correction. In this paper, we introduce a formal debugging approach based on static slicing and dynamic ranking methods to derive a reduced ordered set of potential error locations. In addition, to speed up finding true errors in the presence of multiple design errors, error candidates are sorted in decreasing order of their probability of being an error. After that, a mutation-based technique is employed to automatically correct bugs even in the case of multiple bugs. In order to evaluate the effectiveness of our approach, we have applied it to several industrial designs. The experimental results show that the proposed technique enables us to locate and correct even multiple bugs with high confidence in a short run time even for complex designs of up to several thousand lines of RTL code.

In this paper, we introduce a formal and scalable debugging approach to derive a reduced ordered set of design error candidates in polynomial datapath designs. To make our debugging method scalable for large designs, we utilize a Modular Horner Expansion Diagram (M-HED), which has been shown to be a scalable high level decision model. In our method, we extract data dependency graphs from the polynomial datapath designs using static slicing. Then we combine backward and forward path tracing to extract a reduced set of error candidates. In order to increase the accuracy of the method in the presence of multiple design errors, we rank the error candidates in decreasing order of their probability of being an error using a proposed priority criterion. In order to evaluate the effectiveness of our method, we have applied it to several large designs. The experimental results show that the proposed method enables us to locate even multiple errors with high accuracy in a short run time.

This paper presents an off-line interconnect test methodology that implements the MDSI (Maximal Dominant Signal Integrity) crosstalk fault model. The test methodology consists of MDSI test pattern generators and response analyzers that are incorporated into the IEEE BS 1149.1 Standard on the two sides of an interconnect. This work is the first in implementing MDSI hardware structure. Our method is compared with hardware structures implementing MA interconnect tests.

Loss of signal integrity in today's deep sub-micron designs puts communication links at a higher risk of permanent or more frequent intermittent faults. This results in performance and reliability reduction. This paper presents an online interconnect BIST method that applies to a hybrid serial/parallel communication scheme. The proposed BIST method is implemented by a simple extension to the boundary scan standard, which facilitates online testing methodology with negligible hardware overhead. The online hardware works in the idle state of the Boundary Scan TAP controller. The proposed method includes fault detection and diagnosis phases. Moreover, for error handling, it uses the same test hardware added to the communication interface. It effectively reuses the existing boundary scan structure to act as a signature generator, an error detector and locater for testing interconnects, and an error handling mechanism. Our method can detect about 90% of the interconnect faults after six block transfers.