Abstract Capturing fine‐grained hand‐object interactions is challenging due to severe self‐occlusion from closely spaced fingers and the subtlety of in‐hand manipulation motions. Existing optical motion capture systems rely on expensive camera setups and extensive manual post‐processing, while low‐cost vision‐based methods often suffer from reduced accuracy and reliability under occlusion. To address these challenges, we present DexterCap, a low‐cost optical capture system for dexterous in‐hand manipulation. DexterCap uses dense, character‐coded marker patches to achieve robust tracking under severe self‐occlusion, together with an automated reconstruction pipeline that requires minimal manual effort. With DexterCap, we introduce DexterHand, a dataset of fine‐grained hand‐object interactions covering diverse manipulation behaviors and objects, from simple primitives to complex articulated objects such as a Rubik's Cube. We release the dataset and code to support future research on dexterous hand‐object interaction. Project website: https://pku-mocca.github.io/Dextercap-Page/

With the significant progress of large reasoning models in complex coding and reasoning tasks, existing benchmarks, like LiveCodeBench and CodeElo, are insufficient to evaluate the coding capabilities of large language models (LLMs) in real competition environments. Moreover, current evaluation metrics such as Pass@K fail to capture the reflective abilities of reasoning models. To address these challenges, we propose ICPC-Eval, a top-level competitive coding benchmark designed to probing the frontiers of LLM reasoning. ICPC-Eval includes 118 carefully curated problems from 11 recent ICPC contests held in various regions of the world, offering three key contributions: 1) A challenging realistic ICPC competition scenario, featuring a problem type and difficulty distribution consistent with actual contests. 2) A robust test case generation method and a corresponding local evaluation toolkit, enabling efficient and accurate local evaluation. 3) An effective test-time scaling evaluation metric, Refine@K, which allows iterative repair of solutions based on execution feedback. The results underscore the significant challenge in evaluating complex reasoning abilities: top-tier reasoning models like DeepSeek-R1 often rely on multi-turn code feedback to fully unlock their in-context reasoning potential when compared to non-reasoning counterparts. Furthermore, despite recent advancements in code generation, these models still lag behind top-performing human teams. We release the benchmark at: https://github.com/RUCAIBox/ICPC-Eval

Achieving autonomous navigation and positioning for UAV through computer vision technology has emerged as a key focus and hot topic in current research. The precise matching of UAV images is crucial for realizing this functionality. However, the intrinsic difference between satellite images and UAV images resulted in the sub-optimal performance of traditional matching algorithms. Although the depth-local feature matching of linear Transformers has demonstrated superior hierarchical matching capabilities in UAV image matching, the lack of fine local interactions between pixel tokens restricts their ability to extract highly accurate and localized correspondences. To address the limitations of existing linear Transformer matching algorithms, this paper proposes a novel method called MixFormer, a Mixed Attention Matching Transformer for UAV image feature matching. The algorithm comprises two main aspects: firstly, it introduces a hierarchical feature matching attention framework that operates attention at different scales, integrating global attention and local attention to achieve global context awareness and fine-grained matching, thereby enabling efficient and compact implementation. Secondly, it introduces a feature transformation module for transitional Convolutional Neural Network (CNN) to extract features with full receptive fields. Experimental results on benchmark tests confirm the effectiveness and efficiency of the proposed technique.

Open-domain question answering extract the answer for a question from a large scale corpus, which typically employs ranker to filter irrelevant paragraphs. As traditional retrieval approaches based on statistical characteristics, neural ranking model has gradually become a popular choice for filtering as its capacity of semantic features extraction. But massive corpus request high performance for filtering efficiency. Thus, acceleration of textual encoding by neural model is worthy of attention and there are many achievements on various of perspectives. Inspired by reading habit of human, this paper presents a novel neural ranker on sentence-level jump encoding which can better skip those irrelevant sentences than existing neural models. When people browsing text with questions, they tend to find the key sentence based on heuristic information of question and current reading. And our sentence-level jump encoder works in a similar way which can effectively and accurately locate key sentences for question. We evaluate our neural ranker on long paragraph setting of Quasar-T dataset, our method achieves significant improvements on both ranking acceleration and ranking accuracy, as well as surpass other question answering baselines on the whole question answering results.

Question Generation (QG) aims to construct questions from given text automatically. Recently, QG has received widely concerned. The mainstream method is still based on the fixed sequence generation model of Seq2Seq model, and few people consider the influence of generation order in the result. In this paper, we present a novel Reinforced Attention Decoder Neural Network for the QA-SRL task. First, our model draws on the idea of the reinforcement learning algorithm with baseline, which is using the accuracy of each slot and sentence as the reward, updating the Policy Network to predict the optimal generation order. Second, we apply the Attention mechanism on the baseline to get more relevant information about the entire sentence. Addition experiments explore that distilling knowledge from RAD (the teacher) model to guide RAD-Reborn model (the student) training can achieve better performance. Extensive experiments on QA-SRL Bank 2.0 show that our model outperforms previous systems of all of the evaluation metrics. In particular, the metric EM (Exact Match) increased significantly by over 3%.

Random testing has been widely used in both software and hardware testing areas for years, which is applied as black box testing in software testing. This paper takes advantage of the common features of hardware and software random testing, applying the new concept of the maximum distance among test patterns called Quasi Perfect Maximum Distance Test Sequence (QPMDTS) into software. It is an effective extension from the hardware point of view to fit software testing by using some suitable transformations and improvements so that the random testing procedure can be greatly accelerated. A number of experiments on 39 mutant versions of benchmark program and empirical experiments on four subject programs from numerical recipes have been completed and the favorable results have shown the real effectiveness of the proposed method compared with other random testing techniques. It concludes that the proposed method of test cases generation for software can not only bring higher fault coverage but also a lower test cost compared with the conventional software random testing.

Random testing, having been employed in both hardware and software for a long time, is well known for its simplicity and straightforwardness, in which each test is selected randomly regardless of the tests previously generated. However, traditionally, it seems to be inefficient for its random selection of test patterns. Therefore, a new concept of quasi-best distance random testing is proposed in the paper to make it more effective in testing. The new idea is based on the fact that the distance between two adjacent selected test vectors in a test sequence would greatly influence the efficiency of fault testing. Procedures of constructing such a testing sequence are presented and discussed in detail. The new approach has shown its remarkable advantage of fitting in most circuits. Experimental results and mathematical analysis of efficiency are also given to assess the performances of the proposed approach.

Software reliability is one of the important attributions of dependable systems. A number of software reliability models have been developed by now, but few of them take object-oriented features into account. Nowadays, more and more software systems are developed in object-oriented technology and object-oriented programming languages contain new language features, most notably inheritance, polymorphism, and dynamic binding which have a strong impact on the reliability of software. In this paper, we propose an accurate model for object-oriented software reliability estimation. The central idea of the strategies proposed is to incorporate the influence factors of complexity of the software under test and the test effectiveness into the object-oriented software reliability model so as to make the software reliability model more adequate and accurate to the real situation for object-oriented software. Results from substantial experiments have shown the rationality and usefulness of the new model.

In this paper, we propose a synthesis model for software reliability. For the time being, the assumptions that the architecture-based measurement makes do not address the accurate reliability of components in software, resulting in inaccuracy or even incorrectness in evaluating the software reliability. Therefore, we propose a new reliability measurement based on the software architecture, the complexity and the degree of component importance in software. The central idea of the strategies proposed in this paper is to incorporate the above three reliability measurements into one software reliability model so as to make the software reliability model more adequate and fit to the real situation.

In this paper a new technique for designing finite state machines with concurrent error detection is presented using convolutional codes. In order to correct the fault, we propose a novel scheme which can not only detect but also correct errors occurred in FSM transition. More specifically, we demonstrate how the checker using maximum likelihood decoding can correct single-bit error and get 3dB higher of asymptotic coding gain than previous techniques, also we analysis bit error rate performance for Viterbi decoding of convolutional code. Moreover, we realize the IP core of the self-checking module by SMIC 0.25 mum CMOS technology and also simulate its function in FPGA .

Based on random testing, this paper introduces a new concept of orderly random testing for both hardware and software systems. Random testing, having been employed for years, seems to be inefficient for its random selection of test patterns. Therefore, a new concept of pre-determined distance among test vectors is proposed in the paper to make it more effective in testing. The idea is based on the fact that the larger the distance between two adjacent test vectors in a test sequence, the more the faults will be detected by the test vectors. Procedure of constructing such a testing sequence is presented in detail. The new approach has shown its remarkable advantage of fitting in with both hardware and software testing. Experimental results and mathematical analysis are also given to evaluate the performances of the novel method.

In this paper, we discuss the major weaknesses of the software reliability measurements currently used and propose a new model of software reliability estimation. For the time being, the software reliability models are employed far from ubiquitous. As a national research project, we propose some strategies of improving the software reliability measurement. The central idea of the strategies proposed in this paper is to incorporate the influence factors of complexity of the software under test and the test effectiveness into the software reliability models so as to make the software reliability models more adequate and accurate to the real situation. Results from substantial experiments have shown the rationality and usefulness of the new model.

Software reliability is one of the important attributions of dependable systems. However, for the time being, the assumptions that software reliability measurement makes do not deal with some important factors that influence the accuracy of the software reliability models such as the complexity of the software and the effectiveness of test suite, resulting in inaccuracy or even incorrectness in evaluating the software reliability. Therefore, in this paper, we propose some practical strategies in order to improve the accuracy of software reliability measurement. The idea of the strategies presented in this paper is to incorporate the important factors related to the precision of software reliability measurement into reliability models, which mainly include complexity of software and the test effectiveness, making the software reliability models more adequate and accurate to the real measurement. Experimental results based on five programs selected have shown the feasibility and usefulness of the new approach.

In this paper a pipelined carry-dependent sum adder with the self-checking structure is proposed. The adder includes four 8-bit carry-dependent sum adder (CDSA) , a 4-bit block carry look-ahead unit (BCLU) and a parity checker. The necessary area of the proposed adder is only about 3.85% over the traditional ripple carry adders, while the sum of the traditional adders is delayed by 39.2% with respect to the proposed adder for 32-bit implementation

Although mutation is one of the practical ways of enhancing the effectiveness of the test cases to be applied to an application under test, it could be sometimes infeasible for there being too many assumed faults and mutants to be operated in a larger scale system so that the mutation operating becomes time-consuming and even prohibited. Therefore, the number of faults assumed to exist in the software under test should be reduced. Fault collapsing is a common way of reducing the number of faults in hardware testing. However, this strategy can now be well implanted into the area of software testing. In this paper, we utilize the concept of fault dominance and equivalence, which has long been used in hardware testing, for revealing a novel way of reducing the number of faults assumed to hide in software systems. Once the number of faults assumed in software is decreased sharply, the effectiveness of mutation testing would be greatly enhanced. Examples and experimental results are presented to illustrate the effectiveness and the helpfulness of the technology proposed in the paper

Traditionally, parity testing is one of the exhaustive testing techniques, which needs applying all possible input combinations without need of knowing the implementation of the circuits under test. The way seems to be less interesting to the test engineers in the past days, mainly due to the reasons of its low efficiency and time-consuming, which became a barrier as the number of input lines gets growing. However, in this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing: The main idea of this work is just to change an exhaustive parity testing into a non-exhaustive one, referring to as pseudoparity, and then followed by a pseudo-parity testable design to help realize the new way of pseudo-parity testing. The technique of pseudo-parity testing presented in this paper can now be used in testing for a large scale of combinational circuit. Experiment results are given to show its facility and usefulness.

This paper, based on the well-known syndrome testing, introduces some new concepts of so called high-order syndrome testing for VLSI circuits to improve the efficiency of the method. Syndrome testing has been developed for years in the areas of testing. It is known that the syndrome testing is one of the exhaustive ways of testing, which could be one of the main barriers to widespread acceptance of the exhaustive way of testing since it could be time-consuming when the number of input variables is growing. In this paper, a novel concept called partial syndrome testing is presented in which the traditional syndrome is divided into several parts such that it contains at least two advantages comparing to that of traditional one: (1) increasing the fault coverage and (2) reducing the testing time, therefore, to improve the efficiency of the testing. Procedure of deriving the partial syndrome is described in detail. Experimental results on benchmark as well as other circuits are also given to evaluate the performances of this new approach.

In VLSI chips, the detail circuit implementation is always unknown; only the functional behavior could be known to the users. In this paper, we present a systematic technique for detecting and locating of both stuck-at and bridging faults on the primary input and output lines based on the functional behavior of the circuit being tested. The proposed technique could be quite helpful for both the academic and industrial users of VLSI chips for their testing of the stuck-at and bridging faults and verifying the functions before the chips are applied. Algorithms and experimental results of computer implementation of the scheme are reported.

Software testing has been a hard nut in the testing area for its complex and time-consuming nature. Taking advantage of mature technologies in hardware testing, we proposed a new approach to developing a new dimension of software testing called build-in-self-test (BIST) for software, which has long been applied in hardware testing as well as design for testability. This idea of testing methods from hardware is just to alleviate the burden of testing for software by transferring some testing work onto the programmer during programming so that the programmer and the tester can work together. Some new ideas are presented for further work.

Random testing has been used for years in both software and hardware testing. It is well known that in random testing each test requires to be selected randomly regardless of the tests previously generated. However, random testing could be inefficient for its random selection of test patterns. This paper, based on random testing, introduces the concept of Maximum Distance Testing (MDT) for VLSI circuits in which the total distance among all test patterns is chosen maximal so that the set of faults detected by one test pattern is as different as possible from that of faults detected by the tests previously applied. The procedure for constructing a Maximum Distance Testing Sequence (MDTS) is described in detail. Experimental results on Benchmark as well as other circuits are also given to evaluate the performances of our new approach.

In this paper, some new approaches are presented to deal with the dilemma we are facing in using parity testing: (1) proposing a method of turning a parity untestable circuit into parity testable (2) presenting a scheme of replacing the exhaustive testing with nonexhaustive method. The parity testing may resume its position by using some new technologies including the techniques presented.

Within this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to confirm the validity and usefulness of this approach.

Within this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit, choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. Some objective quantitative measures are used in making such choice. Such measures are so important to the analysis of algorithms that become the subject of this work.

This paper introduces the concepts of random-like testing. In a random-like testing sequence, the total distance among all of the test patterns is chosen maximal so that the sets of faults detected by one test pattern are as different as possible from that of faults detected by the tests previously applied. Procedure of constructing a random-like testing sequence (RLTS) is described in detail. Theorems to justify the effectiveness and helpfulness of the procedure presented are developed. Experimental results on benchmark circuits as well as on other circuit are also given to evaluate the performances of our new approach.

Test generation algorithms are being developed with the continuous creation of incredibly sophisticated computer systems. Although dozens of algorithms have been proposed to cope with these issues, there still remains much to be desired in solving such problems as to determine: which of the existing test generation algorithms could be the most efficient for some particular sequential circuits because different algorithms will be better in different circuits; which testability parameters will have the most or the least influences on test generations so that the designers of circuits can have a global understanding during the designing stage. Testability predicting methodology for sequential circuits using a neural network model has been presented, which a user usually needs for analyzing his/her own circuits and selecting the most suitable test generation algorithm from all the possible algorithms they have, and which a designer for VLSI circuits always needs for making his/her circuits being designed more testable.

Of all the developments of testable as well as reliable designs for computing systems, test generations for sequential circuits are usually viewed as one of the hard nuts to be solved in terms of complexity and time-consumption. Although some dozens of algorithms have been proposed to cope with these issues, much still remains to be desired in solving such problems so as to determine: (1) which of the existing test generation algorithms could be the most efficient for some particular circuits; (2) which parameters will have the most or least influences on test generations. For this purpose, a testability forecasting method for sequential circuits using regression models has been presented which a user usually needs for analyzing their own circuits and selecting the most suitable test generation algorithm from all possible algorithms available. Some examples and experimental results are also provided in order to show how helpful and practical the method is.

The testing of bridging faults (short circuits) has become increasingly important with the increasing density in VLSI (very large scale integration) chips. Yet very little work has been done in this area. In this correspondence, based on a two-state sequential machine model, we present the conditions for a circuit with feedback bridgings to oscillate and to exhibit stable sequential behavior. It is shown that only two test patterns are sufficient to detect feedback bridging faults between input and output lines of a general combinational network. We derive a simple equation to generate test patterns for detecting feedback bridging faults among internal lines of a general combinational network.