Scene text detection is a fundamental component of optical character recognition, document intelligence, assistive technologies, multilingual content retrieval, and multimodal perception systems. However, accurately detecting text that is curved, stylized, densely packed, or small-scale in natural scenes remains challenging—limiting the reliability of text-dependent vision systems in real-world applications. In this paper, we propose a Query vector guided Multi-scale Text Detection algorithm (QMTD) that dynamically generates the initial query vectors for the transformer decoder using a query embedding initialization module. By extracting the initial query vectors from the pixel features of the input feature map, QMTD improves the model’s generalization ability. Additionally, an attention region guidance module is introduced to exploit multi-layer decoder features in the transformer to direct subsequent computational processes, which allows for the step-by-step refinement of the predicted results across multiple decoder layers, accelerating training while improving model performance. Finally, QMTD incorporates a multi-scale feature enhancement module, which uses high-resolution feature maps to improve segmentation precision and low-resolution feature maps to balance the computational time required. Evaluations on CTW1500, Total-Text, and ICDAR2015 benchmarks demonstrate that QMTD achieves competitive or state-of-the-art H-mean, converges faster than the DTTR baseline during training, and maintains robust performance across curved and multi-oriented text scenarios. These findings collectively establish QMTD as a highly effective and practical solution for robust scene text detection.

Memristors offer advantages in terms of high speed, high integration density, and non-volatility, making them a promising option for efficient logic applications. Recent works have explored the design methodology for ternary logic in memristor-based computing-in-memory (CIM) systems. However, existing methods require a large number of devices and are susceptible to noise interference. To address these issues, this work proposes a reliable in-memory computing paradigm for balanced ternary logic based on complementary resistive switch (CRS), which can be considered as two anti-serially connected memristors. Six balanced ternary logic gates are designed based on the proposed method, which support parallel operations when integrated into the CRS crossbar array. To demonstrate the efficiency of the proposed method, a 1-tri full adder is designed by using the proposed logic gates. The feasibility of the design is verified by Cadence Virtuoso using the Voltage Threshold Adaptive Memristor (VTEAM) model. The Monte Carlo simulation of the full adder verifies the reliability of the proposed method. Compared to existing methods, both the operation steps and area overhead are reduced using the proposed approach.

To improve test data compression efficiency, the order of the scan unit need be adjusted, which indirectly changes the content of the test pattern. Scan chain partitioning is a common method that utilises this concept. However, current scan chain partitioning methods can still be optimised in terms of entropy and test data compression efficiency, and lack universality. To enhance the efficiency of code-based compression efficiency, we propose a scan slice reordering algorithm that minimizes entropy. This algorithm first calculates the rank of each scan slice or column vector of the test set, and then dynamically adjusts the order of the scan slices according to the descending order of these ranks in the pursuit of minimizing the entropy of the test set. By iterating through this process, the optimal position of each scan slice in the test set is ultimately determined. Compression experiments should be performed on all test patterns using different code-based schemes. This not only reduces the entropy of the test set but also significantly improves the efficiency of different codes. Compared to traditional scan chain partitioning method, FDR encoding achieved an average compression ratio increase of 6.16%, and RL-Huffman encoding achieved an average compression ratio increase of 4.96%. The experimental results demonstrate that our proposed algorithm is feasible, effective, and universal.

Memristors have the merits of small area, low power consumption, and non-volatility, which are eminently suitable for storing the weights of neural networks. However, stuckat faults (SAFs) and variations in memristor devices significantly degrade the recognition accuracy of ternary memristive neural networks (TMNNs). In response to this issue, we propose a dynamic weight quantization-based fault-tolerant training method to obtain high recognition accuracy for TMNNs with SAFs and variations. A dynamic weight quantization function is proposed by a column-wise weight quantization method considering these faults, where each column has a different symmetric threshold of a TMNN. A hardware activation function is implemented by setting the bias voltages of amplifiers and inverters in memristive crossbar arrays (MCAs). Experimental results show that we can achieve the best recognition accuracy in image classification on MNIST for TMNNs with SAFs and variations. The average recovered accuracy for various SAF ratios is 98.7%, which demonstrates the practicality of our method. Compared with the state-of-the-art methods, the accuracies of our proposed method are 0.88% more when there are 40% of SAFs, 0.87% more when the standard deviation of variations σ is 0.2, 1.7 % more when the SAF ratio is 20% and σ=0.2. We also evaluate our method using VGG-small on CIFAR-10 and U-Net for image segmentation on Portrait to show its effectiveness.

Recently, most transformer-based approaches have achieved considerable success on vision tasks, even better than those with convolution neural networks (CNNs). In this paper, we present a novel transformer-based model, named detecting text with transformers (DTTR), for scene text detection. In DTTR, a CNN backbone extracts local connectivity features and a transformer decoder captures global context information from a scene text, effectively. In addition, we propose a dynamic scale fusion (DSF) module that can fuse multiscale feature maps dynamically, thus significantly improving the scale robustness and rendering powerful representations for subsequent decoding. Experimental results show that DTTR achieves 0.5% H-mean improvements and 20.0% faster in inference speed than the SOTA model with a backbone of ResNet-50 on MMOCR. Code will be released at: https://github.com/ahsdx/DTTR.

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced March algorithm is designed to detect all the modeled faults. In one resistor crossbar with$N$memristors, the enhanced March algorithm requires$8N$write and$7N$read operations with negligible hardware overhead. To reduce the test time, a March RC algorithm is proposed based on read operations with new reference currents, which requires$4N+2$write and$6N$read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement March RC algorithm with a little area overhead.

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption in 1R crossbars, is used as a large-scale memory system. In this paper, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers defined faults caused by electrical defects. The test time of the proposed test algorithm is reduced significantly compared with previous test algorithms that are enhanced for CMOL architecture.

Code-based test vector compressions are the most capable of testing current SOCs consisted of a large number of IP cores because they do not need the structure information of the cores. However, the compression ratios of this kind of compression approaches are often lower than that of other compression methods, such as linear-decompression-based schemes and broadcast-scan-based schemes. In this paper, we propose a novel method that can greatly improve the compression ratios for code-based test vector compression techniques with affordable overheads. The method decomposes an original test set to a prominent component set and a residue set using Hadamard transform. The prominent component set can be generated easily by an additional on-chip TPG, whereas the residue set can be compressed efficiently. When testing is conducted, the compressed residue is transmitted from the tester to the CUT and decompressed by a decompressor. At the same time, the prominent component set is produced by the on-chip TPG, and then composed with the residue to restore the original test set that is at last applied to the CUT. The experimental results for seven different code-based methods on some largest ISCAS'89 circuits show that the total average compression ratio rises from 60.76% to 77.74%. The compression ratio will be further improved to 85.39% if a fault simulation tool can be used. Primary results on some ITC'99 circuitries are also provided.

With the exponential increase of transistor counts, scan design encounters several problems such as large test data volume, long test application time and high test power. In this paper, we propose a new method to reduce test data volume, test application time and also average and peak power during test. The proposed method is based on a scan chain disabling technique where only one internal sub scan chain is active at a time. Though our method makes a sacrifice of test generation time, instead, we can achieve reduction of test data volume, test application time and test power together. Experimental results show the effectiveness of the proposed method.

This paper proposes a novel power-aware scan architecture: DCScan. In this architecture, the compatible scan cells are grouped into the same segment. Test data propagation in DCScan includes two parts: data copying and data shifting. There is no scan shift-in transition during data copying. Experimental results show our approach can achieve low test power, low wiring overhead and low test response data volume.

A new built-in-self-test scheme, referred to as Test Vectors Applied by Circuit-under-Test (TVAC), is proposed in this paper. As the point of view of the paper, Circuit-under-Test (CUT) is no longer only regarded as a test object, but also a kind of available resources. By feedback connecting some of the CUTpsilas interior nodes to the input terminals, the method can generate a test set with low area overhead, short test application time, and enable at-speed testing. A ldquofeedback groupingrdquo search algorithm is presented for a given CUT and its test set. The experimental results on ISCAS85 benchmark circuits and MinTest test sets demonstrate that the proposed scheme not only can achieve almost 100% single stuck-at fault coverage, but also has an average 54.1% reduction in test pattern length compared with LFSR reseeding approaches, and an average 6.1% extra area overhead over the area of the largest five CUTs. The percentage of extra area overhead is not sensitive to the size of the CUT.

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our approaches.