Physical Unclonable Functions (PUFs) are vital for secure hardware authentication due to their intrinsic uniqueness. RRAM-based PUFs offer advantages such as compactness, low power, and CMOS compatibility, but suffer from reliability issues under environmental stress such as temperature and aging. This work proposes a self-checking RRAM-based PUF architecture using a resistance-delay mapping method to generate reliability-quantified challenge-response pairs (CRPs). A configurable Delay Amplification Chain (DAC) converts device-to-device(D2D) resistance variations into measurable timing differences, ensuring stable operation from -55°C to 125°C and ± 10% VDD fluctuations. A built-in self-checking mechanism filters unstable CRPs via complementary delay biases during the dark bit filtration stage, reducing bit error rate (BER) from 5.2% to 0.77%. A hierarchical framework further classifies CRPs into 11 reliability levels, enabling adaptive key management. Implemented in 180nm CMOS/RRAM technology, the design achieves 49.61% inter-chip and 49.80% reconfig Hamming distances across 50 instances, showing strong uniqueness and reconfigurability. No BER degradation was found in 10-year aging simulations. The design meets NIST SP800-22 randomness standards and offers a scalable and entropy-aware solution for IoT security.

Vision Transformers (ViTs) are new foundation models for vision applications. Edge-deploying ViTs to realize energy-saving, low-latency, and high-performance dense predictions have wide applications, such as autonomous driving and surveillance image analysis. However, the quadratic complexity of the self-attention mechanism renders ViTs slow and resource-intensive, particularly for pixel-level dense predictions that involve long contexts. Additionally, the pyramid-like architecture of modern ViT variants leads to an unbalanced workload, further reducing hardware utilization and decreasing the throughput of conventional edge devices. To this end, we propose an algorithm-hardware co-optimized edge ViT accelerator tailored for efficient dense predictions. At the algorithm level, we propose a decoupled chunk attention (DCA) mechanism implemented in a pipelined manner to reduce off-chip memory access, thereby enabling efficient dense predictions within limited on-chip memory. At the architecture level, we introduce a hybrid architecture that combines SRAM-based computing-in-memory (CIM) and nonvolatile RRAM storage to eliminate extensive off-chip memory access, with a fusion scheduling to balance workloads and minimize intermediate on-chip memory access. At the circuit level, a bit/element two-way-reconfigurable CIM macro is proposed to improve hardware utilization across pyramidal ViT blocks with varied matrix sizes. The experimental results on object detection, semantic segmentation, and depth estimation tasks demonstrate that our design can efficiently process patch lengths up to 16384 with a speedup of 18.5×-217.1×, a reduction in memory accesses of 1.7×-7.4×, and an improvement in energy efficiency of 1.8×, under less than 1% performance degradation.

Multimodal Transformer (MMT) algorithms have become the state-of-the-art for multimodal tasks such as image captioning. The Encoder-Decoder (E-D) structure, consisting of Encoder, Decoder-causal, and Decoder-cross components, provides a flexible and effective framework for multimodal tasks. However, previous accelerators mainly focus on the dataflow and hardware optimization of the Encoder, which fails to accelerate the entire E-D structure efficiently. There remain three challenges: 1) the lack of pipeline and multicore optimization at the module, layer, and E-D level; 2) the Decoder-causal and Decoder-cross computations have lower arithmetic intensity compared to the Encoder, requiring a better solution for the varying arithmetic intensities; and 3) the autoregressive algorithm in Decoder-causal leads to redundant KV Cache accesses and considerable idle power. In this paper, SHMT, an SRAM and HBM hybrid computing-in-memory (CIM) architecture, is designed to efficiently support multimodal Transformers with three key contributions: 1) a multi-level pipelined multicore scheme, including pipeline optimization across E-D layer-head-module levels and a multicore network-on-chip (NoC) architecture, to reduce inference latency and off-chip accesses; 2) a heterogeneous SRAM-HBM architecture, utilizing high-density HBM-CIM for low-arithmetic-intensity (LAI) parts and high-performance SRAM-CIM for high-arithmetic-intensity (HAI) parts; and 3) by integrating KV Cache with zero-padding in SRAM-CIM, SHMT eliminates redundant read-write operations in KV Cache, reducing idle power consumption. Experiment results show that SHMT achieves 212× speedup, reduces energy consumption by 208×~2000× per token, and achieves 13.3× higher energy efficiency compared to NVIDIA A100 GPU.

This article presents a mixed-signal general-purpose computing core designed to support real-time inference applications in always-on low-power pulsewidth modulation (PWM) CMOS image sensors (CISs), functioning as a processing-in-sensor (PIS) circuit. This core can be integrated into the columns of CISs to perform low-power edge processing on images, without affecting the pixel fill factor and imaging quality. It employs a coordinated mechanism in which motion detection (MD) triggers the activation of feature extraction (FE), thereby achieving an organic integration of MD and FE functionalities, and maximizing the system’s power efficiency. MD is implemented via in-column frame difference (FD), while FE is performed using a programmable-weight$3\times 3$convolution, a rectified linear unit activation function, and a$2\times 2$max-pooling (MP) operation. Both functionalities are computed based on real-time PWM signals from the CIS and the principle of current integration, with partial circuit reuse achieved through different switching operations. A 0.8-V computing core prototype, with an area of 720 × 272$\mu$m, was fabricated and verified using 0.18-$\mu $m standard CMOS technology. The experimental results at an image frame rate of 250 fps demonstrated an average power consumption of$5.23~\mu $W for MD and$17.53~\mu $W for FE. The prototype core computes the first two layers of an ultra lightweight convolutional neural network (CNN) for the task of MNIST digit classification, achieving an accuracy loss of only 0.86% compared to the ideal scenario. This analog computing core can be used in multimode, low-power, edge-intelligent vision sensors.

AdderNet is an innovative neural network (NN) structure that substitutes multiplications with additions in convolutional operations, while computing-in-memory (CIM) is an efficient architecture that tackles the memory bottleneck for von Neumann architectures. Previous work has explored the SRAM-based CIM AdderNet circuits and demonstrates high energy efficiency. However, it still suffers low storage density, repetitive readout, and redundant comparisons. In this brief, an RRAM-based CIM macro is proposed for efficient AdderNet with the following innovations. First, RRAM cells are adopted to replace SRAM for high-density weight storage. A low-power readout and hold circuit is proposed to save redundant read power of weight data held for multiple cycles. Second, an 8-bit comparator with an early-stop strategy is proposed to compare 8-bit activations and weights in one cycle. Third, an activation (ACT) differential strategy is proposed to reduce redundant comparisons. The proposed 28-nm RRAM CIM macro achieves 12.8-TOPS/mm2peak area efficiency and 126-TOPS/W peak energy efficiency, which is$3.0\times $and$1.2\times $compared with the state-of-the-art AdderNet CIM macro.

The big data era has facilitated various memory-centric algorithms, such as the Transformer decoder, neural network, stochastic computing (SC), and genetic sequence matching, which impose high demands on memory capacity, bandwidth, and access power consumption. The emerging nonvolatile memory devices and compute-near-memory (CNM) architecture offer a promising solution for memory-bound tasks. This work proposes a hybrid resistive random access memory (RRAM) and static random access memory (SRAM) CNM architecture. The main contributions include: 1) proposing an energy-efficient and high-density CNM architecture based on the hybrid integration of RRAM and SRAM arrays; 2) designing low-power CNM circuits using the logic gates and dynamic-logic adder with configurable datapath; and 3) proposing a broadcast mechanism with output-stationary workflow to reduce memory access. The proposed RRAM-SRAM CNM architecture and dataflow tailored for four distinct applications are evaluated at a 28-nm technology, achieving 4.62-TOPS$/$W energy efficiency and 1.20-Mb$/$mm2memory density, which shows$11.35\times $–$25.81\times $and$1.44\times $–$4.92\times $improvement compared to previous works, respectively.

Computing-in-memory (CIM) architectures based on various devices, such as resistive random access memory, SRAM, DRAM, etc., have demonstrated promising energy efficiency. Single-device-based CIM chips show different advantages on performance, power, or area metrics under different workload/operators sizes and application requirements. Some nonidealities, such as the write endurance of some nonvolatile devices, also influence the design choices. Motivated by the emerging 2.5-D/3-D chiplet integration, this work aims to combine the advantages of CIM/storage chips based on different devices, and proposes a design exploration framework to combine the advantages of CIM chips based on these devices in a 3-D-stack architecture. This work proposes: 1) an evaluation method for the power, performance, and area metrics of the multichiplet CIM architecture; 2) an abstraction for the single-device-based CIM chiplets and artificial intelligence algorithm operators; and 3) a mapping and optimization strategy to explore the 2.5-D/3-D CIM chiplet set. The effectiveness of the mapping strategy is verified with a small-scale brute-force search. The proposed design exploration framework can help to find a better-multichiplet CIM architecture. Under a simple design case, the proposed 3-D CIM architecture shows$4.68\times $–$53.32\times $energy efficiency compared with the single CIM chip baselines. The abstracted chiplet library is open-source available in the open-sourcehttps://github.com/dai0dai/3D_CIM_Chiplet_Architecture_Exploration.

Super-resolution (SR) task using the convolutional neural network is a crucial task in improving image and video quality. The introduction of the residual block (RB) raises the depth of the algorithm to perform better reconstruction. The processing of the RB leads to a decrease in hardware utilization and frequent off-chip communications. It is hard to apply such algorithms on edge devices with limited performance. Computing-in-memory (CiM) is one promising method to reduce high power caused by massive data movement in multiply-accumulation computation. The algebraic sparsity (AS) is the structured sparsity (SS) optimization for imaging computing. However, it is an unsolved problem to simultaneously realize the texture sparsity (TS) of the image and the SS of the algorithm in the CiM scheme while maintaining high hardware utilization. Thus, we propose a CiM-based SR task accelerator. There are three key contributions: first, a texture-aware workflow and a dynamic grouping CiM engine can concurrently support TS coupling with AS. Second, a macro-level pipeline scheme together with two custom-sized CiM macros and a high reuse-rate Hadamard transformation circuit reaches 91% hardware utilization. Third, a novel weight update strategy is devised to reduce the performance loss induced by the weight updating. The accelerator prototype is fabricated in a 28-nm CMOS. It scores a 22.8-44.3-TOPS/W peak energy efficiency at the voltage supply of 0.54-1.1 V and the operating frequency of 50-200 MHz, indicating 1.8-6.8x higher compared to the state-of-the-art CiM processors.

Transformers have made remarkable contributions to natural language processing (NLP) and many other fields. Recently, transformer-based models have achieved state-of-the-art (SOTA) performance on computer vision tasks compared with traditional convolutional neural networks (CNNs). Unfortunately, existing CNN accelerators cannot efficiently support transformer due to the high computational overhead and redundant data accesses associated with the ‘KQV’ matrix operations in the transformer models. If the recently-developed NLP transformer accelerators are applied to the vision transformer (ViT) models, their efficiency would decrease due to three challenges. 1) Redundant data storage and access still exist in ViT data flow scheduling. 2) For matrix transposition in transformer models, the previous transpose-operation schemes lack flexibility, resulting in extra area overhead. 3) The sparse acceleration schemes for NLP in prior transformer accelerators cannot efficiently accelerate ViT with relatively fewer tokens. To overcome these challenges, we propose$P^{3}$ViT, a computing-in-memory (CIM)-based architecture, to efficiently accelerate ViT, achieving high utilization on data flow scheduling. There are three key contributions: 1) P3ViT architecture supports three ping-pong pipeline scheduling modes, involving inter-core parallel and intra-core ping-pong pipeline mode (IEP-IAP3), inter-core pipeline and parallel mode (IEP2), and full parallel mode, to eliminate redundant memory accesses. 2) A two-way ping-pong CIM macro is proposed, which can be configured to regular calculation mode and transpose calculation mode to adapt to both$\text{Q}\times \text{K}^{\mathrm {T}}$and$\text{A}\times \text{V}$tasks. 3) P3ViT also runs a small prediction network. It prunes redundant tokens to be a standard number hierarchically and dynamically, enabling high-throughput and high-utilization attention computation. Measurements show that P3ViT achieves$1.13\times $higher energy efficiency than the state-of-the-art transformer accelerator and achieves$30.8\times $and$14.6\times $speedup compared to CPU and GPU.

Radio frequency identification technology (RFID) has empowered a wide variety of automation industries, such as logistics and freight transportation. To further promote RFID tags adoption, security, power consumption, and cost have always been issues of general concern. This article presents the first synergy of the RFID tag with embedded resistive RAM (RRAM) array and RRAM-based reconfigurable strong physical unclonable function (R-SPUF). The RRAM not only meets the mass storage and technology downscaling but also renders the ultralow-cost “1-cent RFID tag” more feasible. Moreover, the R-SPUF facilitates multiple initializations until a satisfactory distribution and has strong secure keys benefiting from its reconfigurability that improves both safety and reliability. The complete system operates at 13.56 MHz and is compliant with the ISO14443-A and ISO10373-6 (test) protocols. The RFID tag was fabricated on a 1.1-mm2 die based on the 0.18-$\mu \text{m}$CMOS process. Without resorting to the charge pumps for RRAM read–write operations, the total power consumption is as low as 52.3$\mu \text{W}$, of which the RRAM dissipates$16.2~\mu \text{W}$under a wireless power supply.

As 5G high-speed mobile communications developing rapidly, services and contents that people get from the Internet have been enriched significantly, which necessitates the user equipment (UE) to have least power consumption, reduced latency, enhanced lifetime and better QoS. However, the tail energy of LTE interface on UE leads to low energy efficiency which is caused by applying fixed Radio Resource Control (RRC) inactivity timer. In this paper, we propose a novel approach to eliminate the tail whenever possible and improve the user equipment power efficiency. We design a self-adaptive tool to optimize the LTE RRC inactivity timer for individual users based on user model. Firstly, The tool collects runtime network information from cellular networks and uses machine learning method to predict the session length. Then it adjusts inactivity timer dynamically based on the predicted session length. In addition, we propose an enhanced RRC protocol to support our proposed tool. To demonstrate the effectiveness of our energy-saving tool, we applied it on commercial off-the-shelf phones. Simulation results show the proposed tool can reduce the energy consumption of smart-phone by 27-33.5%.

For Electrocardiogram (ECG) and electroencephalogram (EEG) recording application, this paper proposes an extremely low-power, low-noise analog front-end (AFE). Based on fully-integrated, high-pass, low-noise amplifier and inverter-based, low-power 2ndSigma-Delta modulator, large output swing, excellent power efficiency and noise performance are achieved. The circuit is implemented in 0.13μm 1P8M Mixed-signal technology. The measurement results show in 0.6V power supply, input referred noise is 3.976μVrms and the noise efficient factor (NEF) is 3.658. Max Signal-to-Noise and Distortion Ratio (SNDR) is 66.7dB with 8.4μw power consumption. Compared with previous work, our design has the maximum SNDR and signal bandwidth, which meets the requirement of ECG/EEG recording application.

Hardware Trojans (HTs) are emerging threats for integrated circuits. In this paper, we propose a novel scheme, named LMDet, to detect HTs through distinguishing the “unnaturalness” of HTs from the “naturalness” of normal circuits using the natural language processing technology. The key insight of LMDet is that we find clean circuits tend to be “natural” (i.e., to be highly repetitive in structure) and HTs appear to be “unnatural” (i.e., to be rare in structure) in some sense. LMDet models circuit gates sequentially, using the n-gram language model. Gate sequences from the circuit under detection (CUD) are assessed according to their probability in the model, and lowprobability sequences are marked as suspected Trojan-related gates. Evaluation with benchmarks and industrial circuits shows that LMDet is capable of detecting Trojan logic without the HT-free reference of CUD. LMDet has short execution time on large commercial circuits with acceptable space overhead. It is a promising method in real industry since plenty of HT-free designs are available as training corpus to ensure good statistical effects.

A wide-range tracking technique for clock and data recovery (CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10 −3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10 –12 . The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.

In this paper a full chip implementation of a Mixed-signal hearing aid SoC is presented. The chip integrates Analog Front-End (AFE), Time-Division Multiplexed Power-On-Reset circuit (TDM-POR), Charge Pump (CP), Digital Signal Processing (DSP) platform and Class-D amplifier. Also, the Low-Dropout (LDO) voltage regulators and On-chip oscillator are both integrated to minimize the system overall size. The proposed SoC has been fabricated in SMIC 0.13μm CMOS process. The measurement results show that the peak Signal-to-Noise Ratio (SNR) of AFE is 82dB and peak SNR of Class-D amplifier is 79.6dB. And the DSP platform executes three hearing-aid algorithms of wide dynamic range compression (WDRC), noise reduction (NR), and feedback cancellation (FDC). The total SoC consumes 1.1mA from single 1V supply and occupies 9.3mm2. Finally a prototype of hearing aid device is designed and passes the industrial acoustic test which shows the chip is promising for mass production in future.

A fast-lock-in harmonic-free all-digital delay-locked-loop (ADDLL) in STMicro 32nm CMOS technology is presented. The ADDLL uses a novel complementary delay line with lattice-type delay elements. The complementary line can effectively reduce at most 50% active delay elements than a single line. Less active delay elements make better suppression of supply-induced jitter. The lattice-type delay element is beneficial to high frequency applications because of its small intrinsic delay. The ADDLL employs a 9-bit configurable SAR controller to achieve fast lock. Moreover, it can work in a wide-range application (200MHz ∼ 2GHz) without the harmonic-lock problem of conventional SAR controllers. Under a 1.1V power supply, the ADDLL has a delay resolution of 8 ps and the lock time is 36 cycles at 200 MHz and 24 cycles at 2GHz.

A low power source-synchronous source-series- terminated (SST) transmitter (Tx) in 65 nm CMOS technology is presented. The Tx, comprised of nine data/control channels, a forwarded-clock channel and one PLL, merely dissipates 26.2 mW/channel while exhibiting a 750 mV differential eye height at 6.4 Gbps. The SST drivers can save ¾ output stage power of CML ones, and moreover, the proposed novel topology can independently control impedance self-calibration and equalization. To implement half-rate architecture, the PVT- tolerant PLL provides a pair of quadrature clocks with 2.5 ps rms cycle to cycle jitters running at 3.2 GHz.

This paper presents the design of a 10 Gb/s low power wire-line transceiver in 65 nm CMOS process with 1 V supply voltage. The transmitter occupies an area of 430 mum times 240 mum, consumes 50.56 mW power and has a 5-order programmable pre-emphasis equalizer. The receiver occupies an area of 300 mum times 500 mum. With the novel half rate period calibration clock data recovery (CDR) circuit, the receiver consumes only 52 mW power. The receiver combines a low power wideband programmable continuous time linear equalizer (CTLE) and a 3-order decision feedback equalizer (DFE).

Short-wave together with medium-and longwave broadcasting still has large listenership worldwide. With the newly developed digital system DRM will overcome these reception problems and bring high audio quality, which will change the whole broadcasting scenario. This paper will give an overview of DRM including its development history, the standardization, the receiving technology, the key features and state of the art. The emergence of DRM lights the way of digital radio ahead.