Meng-chou Chang

dblp:48/1383 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-authorSoftware engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Processor architecture and microarchitecture · 84% Electronic design automation · 10% Energy-efficient computing · 6%
Computer graphics and multimedia
1 paper
Rendering · 91% Virtual and augmented reality · 9%

Topics — the 14 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
superscalar processor
0.031996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Enhancing boosting with semantic register in a superscalar processor · ISCA 1992
Exploiting instruction-level parallelism with the conjugate register file scheme · MICRO 1992
Processor architecture and microarchitecture
instruction-level parallelism
0.021996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Exploiting instruction-level parallelism with the conjugate register file scheme · MICRO 1992
Rendering
global illumination
0.011996
Image Shading Taking into Account Relativistic Effects · ACM Trans. Graph. 1996
Rendering
shading
0.011996
Image Shading Taking into Account Relativistic Effects · ACM Trans. Graph. 1996
Rendering
shadow rendering
0.011996
Image Shading Taking into Account Relativistic Effects · ACM Trans. Graph. 1996
Processor architecture and microarchitecture › instruction scheduling
compiler-based scheduling
0.011996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Processor architecture and microarchitecture
instruction scheduling
0.011996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Electronic design automation › high-level synthesis › resource binding
register allocation
0.011996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Processor architecture and microarchitecture › register file
register file design
0.011996
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme · IEEE Trans. Computers 1996
Energy-efficient computing
boosting
0.011992
Enhancing boosting with semantic register in a superscalar processor · ISCA 1992
Processor architecture and microarchitecture
branch handling
0.011992
Enhancing boosting with semantic register in a superscalar processor · ISCA 1992
Processor architecture and microarchitecture › register file
register file organization
0.011992
Exploiting instruction-level parallelism with the conjugate register file scheme · MICRO 1992
Processor architecture and microarchitecture › out-of-order execution
register renaming
0.011992
Enhancing boosting with semantic register in a superscalar processor · ISCA 1992
Virtual and augmented reality
virtual environment
0.011996
Image Shading Taking into Account Relativistic Effects · ACM Trans. Graph. 1996

Methods — techniques the papers use, named apart from their topics

relativistic light propagation modeling · 0.0register allocation · 0.0instruction scheduling · 0.0
YearPublicationVenuePosition
2006 An adaptive search algorithm based on block classification for fast block motion estimation
abstract
This paper presents a new motion estimation algorithm, called the adaptive motion estimation (AME). The AME algorithm exploits the information gathered from the previous frame to derive a parameter, called CF (correlation parameter), and employs CF to classify the blocks in the current frame into potentially dependent blocks and potentially independent blocks. AME applies different motion estimation methods for potentially dependent blocks and potentially independent blocks to achieve better estimation accuracy and lower computational complexity. Simulation results showed that the proposed AME algorithm has both lower computational complexity and higher PSNR than other motion estimation algorithms, such as three-step search (TSS), new three-step search (NTSS), four-step search (4SS), and the NPSA (new predictive search area) algorithm.
Meng-chou Chang, Jung-Shan Chien
ISCAS1
1996 Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme
abstract
This paper introduces a novel superscalar micro-architecture, called IAS-S, and its related software techniques. We treat two basic problems in superscalar machines. First, we seek a feasible hardware platform which allows the compiler to perform more aggressive instruction scheduling. Second, we develop a good way of communication between the instruction scheduler and register allocator to avoid inadequate register allocation resulting in poor instruction schedules. For the first part, IAS-S employs the Conjugate Register File (CRF) scheme to support multilevel instruction boosting so that a greater amount of instruction-level parallelism in a program can be identified at compile time. For the second part, the instruction scheduling in the IAS-S compiler consists of two passes, prepass and postpass, and a scheduling-conflict graph is built for the register allocator during the prepass scheduling. In this manner, the register allocator can take the potential benefit for later postpass instruction scheduling into account and thus prevents inadequate register allocation.
Meng-chou Chang, Feipei Lai
IEEE Trans. Computers1
1996 Image Shading Taking into Account Relativistic Effects
abstract
This article is concerned with creating more realistic images of 3D scenes which are moving relative to the viewer at such high speeds that the propagation delay of light signals and other relativistic effects can not be neglected. Creating images of 3D scenes in relativistic motion might have important applications to science-fiction films, computer games, and virtual environments. We shall discuss the following problems: (1) how to determine the visual appearance of a rapidly moving object, (2) how to determine the apparent radiance of a scene point on a moving object, (3) how to determine the incident irradiance at a scene point coming from a moving light source, (4) how to determine the color of a rapidly moving object, and (5) how to generate shadows when there are relative motions between the viewer, the scenes, and the light sources. Detailed examples are also given to show the result of shading with the relativistic effects taken into account.
Meng-chou Chang, Feipei Lai, Wei-Chao Chen
ACM Trans. Graph.1
1992 Enhancing boosting with semantic register in a superscalar processor
abstract
IAS-S Supports boosting with “semantic register” and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.
Feipei Lai, Meng-chou Chang
ISCA2
1992 Exploiting instruction-level parallelism with the conjugate register file scheme
Meng-chou Chang, Feipei Lai, Rung-Ji Shang
MICRO1