EDBT 2026 Demo / reviewers in the wild / expert
Patricia Desgreys
dblp:48/1604
· DBLP profile ↗
9ranked-venue papers
1as first author
3since 2021 · last 2026
0000-0001-8819-5532ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 3 since 2021Software engineering, systems software and programming languages · 3 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Energy Function Choice for Training Nonlinear Resistive Neural Networks with Equilibrium Propagation
Fatma Zülâl Kiraz, Dang-Kièn Germain Pham, Patricia Desgreys |
ISCAS | 3 |
| 2026 | Piecewise Modeling of RF Power Amplifiers using Derivative Analysis and K-Means Clusterization
Carolina Pedrosa, Pierre Almairac, Peter Rashev, Dang-Kièn Germain Pham, Jean-Christophe Nanan, Patricia Desgreys |
ISCAS | 6 |
| 2024 | Spectral Structure Analysis of FFT-based Digital Predistortion for Wideband 5G ApplicationsabstractIn this paper, a spectral structure analysis for the FFT-based subband digital predistortion is performed. This analysis consists in investigating whether the spectrum of the signal at the output of the power amplifier (PA) shows any particular structuring of the information. Various scenarios are investigated by simulation and validated by experiments, on a real PA. It is found that some spectral zones are more critical than others to maintain good linearization, which makes possible to reduce the requirements of the feedback path. Tayeb H. C. Bouazza, Dang-Kièn Germain Pham, Reda Mohellebi, Patricia Desgreys |
ISCAS | 4 |
| 2018 | A Wideband Mixed-Signal Predistorter for Small-Cell Base Station Power AmplifiersabstractA novel low-power wideband mixed-signal approach to linearize RF power amplifiers (PAs) is presented. The proposed mixed-signal predistorter (MSPD) is based on FIR memory polynomial (FIR-MP) model, where digital FIR filter improves the memory correction performance without any bandwidth expansion and the MP predistorter in analog baseband provides superior linearization. MSPD avoids 5X bandwidth requirement for the transmitter and the power-hungry RF components when compared to digital predistorters (DPDs) and analog-RF predistorters (ARFPDs), respectively. This makes the MSPD solution a very low-power candidate and especially attractive in the context of small-cell base stations. Extracted PA model of a commercial 1 W GaAs HBT PA is linearized over an 80 MHz signal; results prove that the FIR-MP based MSPD in ideal system-level simulations provides an improvement of 14.3 dB and 13.5 dB, in adjacent and alternate channel leakage ratio, ACLR1 and ACLR2, respectively, in comparison with FIR envelope memory polynomial (FIR-EMP) model, used in ARFPD. The impact of various non-idealities are simulated at electrical-level to derive the requirements for the integrated circuit implementation shows that a resolution of 8 bits for the coefficients and a signal path SNR of 60 dB is required to achieve ACLR1 above 45 dBc, with as little as 9 coefficients in the analog domain. Venkata Narasimha Manyam, Dang-Kièn Germain Pham, Chadi Jabbour, Patricia Desgreys |
ISCAS | 4 |
| 2015 | Hardware implementation of all digital calibration for undersampling TIADCsabstractThis paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework. Han Le Duc, Duc Minh Nguyen 0001, Chadi Jabbour, Tarik Graba, Patricia Desgreys, Olivier Jamin, Van-Tam Nguyen 0004 |
ISCAS | 5 |
| 2010 | Merged Digitally Controlled Oscillator and Time to Digital Converter for TV band ADPLLabstractIn this paper we present a merged Digitally Controlled Oscillator DCO and Time To Digital Converter TDC architecture. The DCO is a nine-stage interpolative ring made by NOR cells. It is designed for TV applications and it is implemented in 65nm CMOS process. The oscillator has a large frequency range, from 50MHz to 500MHz, and a 28 × 39/μm2core area. It consumes 1mA from 1.2V power supply, and it has -120dBc/Hz@5MHz phase noise for 420 MHz carrier frequency. The oscillator states are directly used to measure the delay between input and output clocks. The resulting TDC is compact, very economic in power consumption and it has a resolution that is equal to 1/18 of the oscillation period. The DCO and the TDC are used in an All Digital Phase Locked Loop ADPLL. Wissam Altabban, Patricia Desgreys, Hervé Petit, Karim Ben Kalaia, Laure Rolland du Roscoat |
ISCAS | 2 |
| 2008 | A Sigma-delta Bandpass ADC Modelling in Superconducting RSFQ Technology with VHDL-AMSabstractThis paper presents a sigma delta bandpass ADC modelling based on RSFQ (rapid single flux quantum) technology with VHDL-AMS. A Josephson junction model is proposed and simulated based on RCSJ electrical model. Each ADC element is dissociated and simulated to validate its behaviour. We assimilate ADCpsilas comparator which is composed by two Josehpson junctions to an ideal rectangular pulses generator. Pulses duration is directly a physical parameter obtained by technology. We give relations between ADC performance (SNR) to the comparator SFQ pulses form and duration with normalized physical parameters. Rachid Guelaz, Patricia Desgreys, Patrick Loumeau |
FDL | 2 |
| 2006 | Functional Virtual Prototyping Design Flow and VHDL-AMS
Yannick Hervé, Patricia Desgreys |
FDL | 2 |
| 2004 | SoC modelling for virtual prototyping with VHDL-AMS
Patricia Desgreys, Yannick Hervé, Jean Oudinot, S. Snaidero, Mohamed Karray |
FDL | 1 |