This paper proposes a co-design method that integrates the central processing unit (CPU) and resistive random-access memory (ReRAM) crossbar to enhance energy efficiency of Octave convolution. In this method, low-frequency operations within the Octave framework are executed by the energy-efficient ReRAM crossbar, while high-frequency computations, which are crucial for accuracy, are processed by the CPU and results are combined within the CPU to finalize the classification task. Compared to vanilla convolution, for ResNet-50 trained on the CIFAR-10 dataset, this approach reduces the number of CPU operations by 37% while improving accuracy by 4.7%. Compared to traditional Octave convolution, the proposed approach reduces the number of CPU operations by 17% while maintaining accuracy within 2%. Approximately 18.5% of the total operations is executed by the energy-efficient ReRAM in the proposed approach.

A methodology is proposed to enhance the energy efficiency of systolic array based deep neural network (DNN) accelerators by enabling precision- and performance-aware voltage scaling. The proposed framework consists of three primary steps. In the first step, the voltage-dependent timing error probability for each output bit within the processing elements is analytically estimated. Next, these timing errors are injected into DNN models, helping us understand how inference accuracy is affected by lower operating voltages. In the last step, we apply error detection and correction to only select bits within the network, thereby improving inference accuracy while minimizing circuit overhead. For a 256X256 array operating at 0.7GHz and evaluating MobileNetV2 on ImageNet, we can reduce the nominal supply voltage from 0.9V to 0.5V with negligible (0.001%) latency overhead. This reduction in supply voltage reduces the inference energy by 79.4% while degrading inference accuracy by only 0.29%.

Covert communication channels are a significant security threat where the host computer's security policy is bypassed to establish a communication link that can leak sensitive data. Establishing thermal covert channels is feasible because modern processors have accessible temperature sensors that are typically used for dynamic thermal management. In this paper, we first provide an information-theoretic discussion on thermal cover channels and important characteristics such as channel capacity and data modulation methods. Next, we summarize existing thermal covert channel detection methods, including their limitations. We then propose a novel runtime detection method for thermal covert channels where the secret data is encoded via low power programs. Our results demonstrate that the proposed technique can achieve 100% detection accuracy with 0% false positive rate.

Wireless power harvesting has become popular for various Internet-of-Things (IoT)-based devices, such as wireless sensors, radio frequency identification (RFID)-based systems, and implantable devices for healthcare. Since these ubiquitous computing devices are likely to handle confidential information, ensuring their security is critical. In this work, a secure adiabatic logic family, referred to as SEAL-RF, is developed, specifically for RF-powered IoT devices. SEAL-RF is highly energy efficient and resistant against power-based side-channel attacks. Specifically, at the gate-level, the normalized energy deviation (NED) of SEAL-RF is up to$180\times $lower than conventional (unprotected) adiabatic logic, while consuming up to 39% less average energy per transition. Furthermore, the NED of SEAL-RF is up to$5.5\times $lower than an existing secure adiabatic logic, while consuming up to 32% less average energy per transition. A lightweight encryption core based on SIMON algorithm is also designed with the proposed SEAL-RF and conventional adiabatic logic. A correlation power analysis (CPA)-based side-channel attack is mounted on both designs. The secret key for the unprotected SIMON core is retrieved with less than 800 traces whereas the secret key for the SEAL-RF-based SIMON core cannot be retrieved with more than 40K traces. Furthermore, the average power and energy per encryption of the SEAL-RF-based SIMON core is 15.6% lower than the conventional adiabatic logic-based SIMON.

Monolithic 3-D (MONO3 D) integration provides performance and power efficiency benefits over 2-D circuits and, thus, is a potent technology for the design of deep neural network (DNN) accelerators with enhanced energy efficiency. However, high IC temperatures are major challenges for the design of MONO3 D systems. To this end, this article focuses on designing temperature-aware MONO3 D DNN accelerators. We propose a new automated method, called TREAD- M3 D, that provides a near-optimal MONO3 D DNN accelerator architecture in terms of systolic array size, SRAM organization, partition across 3-D layers, and operating frequency, for a given DNN, optimization goal, and temperature constraint. TREAD- M3 D incorporates circuit- and architecture-level models to evaluate the power and performance characteristics of different partitions. Our method reveals valuable insights and enables tradeoff analysis for achieving high energy efficiency in MONO3 D systolic arrays. In comparison to recent works that adopt a fixed partition choice to design MONO3 D DNN systems, TREAD- M3 D yields up to 22% higher energy efficiency. Using TREAD- M3 D, we further demonstrate that temperature unawareness not only leads to infeasible configurations due to temperature violations but also over-estimates energy-delay-product benefits by up to 24%.

No abstract available.

An inductive link based wireless power transfer methodology is described for a smart knee implant designed to continuously monitor the loads on the knee. The primary and secondary coil dimensions and wireless link characteristics are first optimized via an equivalent lumped electrical model. The wireless link is then simulated with more accurate 3D field simulations. The impact of the package and various layers of tissue between the coils on the quality of the link is investigated. The effects of potential misalignments between the coils are also analyzed. When the distance between the coils is 39 mm and the input power to the primary (external) coil is 2.5 W, approximately 0.35 mW of power can be received by the secondary coil that is located within the implant.

Exploiting thermal coupling among the cores of a processor to secretly communicate sensitive information is a serious threat in mobile, desktop, and server platforms. Existing works on temperature-based covert communication typically rely on controlling the execution of high-power CPU stressing programs to transmit confidential information. Such covert channels with high-power programs are typically easier to detect as they cause significant rise in temperature. In this work, we demonstrate that by leveraging vertical integration, it is sufficient to execute typical SPLASH-2 benchmark applications to transfer 200 bits per second (bps) of secret data via thermal covert channels. The strong vertical thermal coupling among the cores of a 3-D multicore processor increases the rates of covert communication by$3.4\times $compared to covert communication in conventional 2-D integrated circuits (ICs). Furthermore, we show that the bandwidth of this thermal communication in 3-D ICs is more resilient to thermal interference caused by applications running in other cores. This reduced interference significantly increases the danger posed by such attacks. We also investigate the effect of reducing intertier overlap between colluded cores and show that the covert channel bandwidth is reduced by up to 62% with no overlap.

We propose an automated method to facilitate the design of energy-efficient Mono3D DNN accelerators with safe on-chip temperatures for mobile systems. We introduce an optimizer to investigate the effect of different aspect ratios and footprint specifications of the chip, and select energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer, we can reduce energy consumption by 1.6x and area by 2x with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.

Logic locking has demonstrated its potential to protect the intellectual property of integrated circuits (ICs). The security strength of logic locking is typically evaluated through functional and structural analysis-based attacks. There is limited work analyzing logic locking techniques' resilience against power-based side-channel attacks. To fill this gap, we propose an attack flow for the correlation power analysis (CPA) attack on the circuits encrypted with transistor-level logic locking. Our case studies indicate that CPA attacks outperform DPA attacks in terms of key recovery rate (KRR). To improve the CPA attack resilience of an existing transistor-level logic locking technique, we propose a logic-cone conjunction (LCC) method to enlarge the key space and reduce the correlation between the locking key and the power consumption of locked circuits. The experimental results show that the LCC method successfully reduces the KRR from 100% to 0% by using cyclic logic structures. The FPGA emulation indicates that the proposed method incurs 2.6% more delay and 1.5% more power consumption than the baseline.

This article focuses on thwarting reverse-engineering attacks and intellectual property (IP) theft by leveraging charge-recycling adiabatic circuits. The adiabatic circuit operation has recently received attention for the Internet-of-Things (IoT) applications due to high energy efficiency and enhanced security characteristics. Such applications typically consist of resource-constrained designs and are often deployed in the field, making them particularly vulnerable to malicious attacks. PhaseCamouflage is a circuit obfuscation technique that leverages the inherent phase differences (PDs) in power supply voltage of adiabatic logic gates and exhibits strong resistance against structural/removal attacks. The proposed method relies on inserting camouflaged PDs in the power supply voltage of subsequent logic gates while still producing a functional netlist. PhaseCamouflage is a unique logic obfuscation technique with low overhead, particularly applicable to pervasive computing applications where both efficiency and security are of primary concern.

This paper discusses the potential of adiabatic circuits for simultaneously achieving energy-efficiency and security. Despite the presence of adiabatic logic for more than six decades, some of the relatively recent improvements demonstrate the significant benefits that adiabatic circuits can provide in niche applications such as RF-powered devices. An overview of these improvements is provided, highlighting the primary design challenges and opportunities related to adiabatic circuits.

A novel regulator topology is proposed to achieve high power efficiency for a wide range of output load current. The proposed topology consists of a switched-capacitor regulator and linear low-dropout (LDO) regulator that operate in a parallel fashion. Switched-capacitor circuit not only achieves voltage conversion, but also performs coarse voltage regulation via frequency modulation. The LDO performs fine regulation. The proposed topology, implemented in 45 nm technology, converts the input voltage of 1.15 V to an output voltage of 0.5 V while supplying up to 120 mA current. 80% power efficiency is achieved at a load current of 80 mA. The efficiency is maintained above 60% as the load current varies between 20 mA and 120 mA. The maximum ripple voltage is less than 50 mV.

Energy efficiency is a critical design objective in deep learning hardware, particularly for real-time machine learning applications where the processing takes place on resource-constrained platforms. The inherent resilience of these applications to error makes voltage scaling an attractive method to enhance efficiency. Timing error probability models are proposed in this article to better understand the effects of voltage scaling on error rates and power consumption of multiply-accumulate units. The accuracy of the proposed models is demonstrated via Monte Carlo simulations. These models are then used to quantify the related tradeoffs without relying on time-consuming hardware-level simulations. Both modern FinFET and emerging tunneling field-effect transistor (TFET) technologies are considered to explore the dependence of the effects of voltage scaling on these two technologies.

Monolithic 3D (Mono3D) is a three-dimensional integration technology that can overcome some of the fundamental limitations faced by traditional, two-dimensional scaling. This paper analyzes the unique thermal characteristics of Mono3D ICs by simulating a two-tier flip-chip Mono3D IC and highlights the primary differences in comparison to a similarly-sized flip-chip TSV-based 3D IC. Specifically, we perform architectural-level thermal simulations for both technologies and demonstrate that vertical thermal coupling is stronger in Mono3D ICs, leading to lower upper tier temperatures. We also investigate the significance of lateral versus vertical flow of heat in Mono3D ICs. We simulate different hot spot scenarios in a two-tier Mono3D IC and show that although the lateral heat flow is limited as compared to TSV-based 3D ICs, ignoring this mechanism can cause nonnegligible error (~4°C) in temperature estimation, particularly for layers farther from the heat sink. In addition, we show that with increasing interconnect utilization (due to the contribution of Joule heating to overall temperature), the on-chip temperatures and the significance of lateral heat flow within the two-tier Mono3D IC also increase. Finally, we discuss potential opportunities in Mono3D ICs to enhance their thermal integrity.

In this paper, a novel local clock gate cluster-aware low voltage clock tree synthesis methodology is introduced. In low voltage/swing clocking, timing closure is a challenging problem due to tight skew and slew constraints. The clock gating makes this problem more challenging due to the high delay mismatch between the gated and the non-gated sinks. The proposed methodology preserves the power savings of the clock gating and exploits low swing clocking to further reduce the power consumption, while maintaining the same skew and slew constraints as the full swing counterpart. Experimental results performed on the large circuits of ISCAS'89 benchmarks operating at 1.5GHz in the 45nm technology node demonstrate that the proposed methodology can provide 38% power savings as compared to a full swing gated clock tree, achieving an additional 12% savings as compared to a low swing non-gated clock tree.

The wirelessly powered adiabatic logic has introduced significant power savings in the design of the computational logic. We explore energy-efficient interfacing of one of the most efficient adiabatic logic families, pass-transistor adiabatic logic (PAL), with RF harvested signal. The interface circuit, signal shaper, transforms the bipolar sinusoidal input voltage to nonnegative unipolar sinusoidal output that serves as the power clock signal for PAL. A theoretical analysis of the operation of the signal shaper is presented and verified using simulations in 65 nm CMOS technology. The designed shaper, when interfaced with 8-bit multiplier implemented using PAL, demonstrates the settling time of a few clock periods and high power conversion efficiency as high as 90%.

Monolithic 3D ICs have vertical interconnects that are comparable in size to local vias, thereby permitting extremely fine-grained vertical integration. SIMON, a lightweight block cipher, is designed and characterized at the Graphic Database System (GDS) level in two types of monolithic 3D design styles: transistor-level, where nMOS and pMOS transistors are split between tiers, and gate-level, where individual gates are partitioned among the tiers. The two 3D implementations as well as a 2D implementation are compared and characterized in terms of area and power. Furthermore, the effect of monolithic intertier vias (MIVs) on power and data integrity is analyzed for each custom 3D design. It is shown that power delivery for transistor-level monolithic 3D design is more challenging since all of the pMOS transistors (that are connected to the supply voltage) are located in the bottom tier where there are limited metal resources due to technology constraints.

A novel glitch-free integrated clock gating (ICG) cell is developed and demonstrated in 45 nm CMOS technology. The proposed cell is more reliable as it produces an uninterrupted gated clock signal in cases where glitches occur in the enable signal during clock transitions. A detailed comparison of the proposed cell with the existing integrated clock gating cells is also presented. Glitch-free operation (and therefore high reliability) is achieved at the expense of larger power and delay, as quantified for 45 nm CMOS technology. The proposed ICG cell is shown to be highly applicable to dual edge triggered flip-flops where existing ICGs fail if there are glitches in the enable signal during clock transitions.

A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints.

In this paper, an alternating current (ac) computing methodology is proposed for integration into wirelessly powered devices, such as radio-frequency (RF) tags and sensor nodes. Contrary to the traditional platforms that integrate direct current (dc)-powered computational logic along with the rectification and regulation stages, in the proposed approach, the harvested RF signal is directly used to power the data processing circuitry by leveraging the charge-recycling and adiabatic circuit theory. A near-field-based wireless power harvesting system with an 8-bit arithmetic logic unit is developed to evaluate the proposed framework. Simulation results in 45-nm technology demonstrate that the overall power consumption can be reduced by up to 16 times as compared to the conventional approach that relies on ac-to-dc conversion and static CMOS logic. This reduction in power enables significant computation capability for the RF-powered devices. Several important characteristics, such as the impact of circuit size on overhead and processing power, impact of voltage scaling on circuit operation, and power consumption, are investigated. Some important design issues and related tradeoffs are also discussed.

A novel framework and related methodologies are described to leverage RF power for building intelligent and battery-free devices with communication and computation capabilities. These passive devices are envisioned to make significant impact for the popular vision of smart dust due to extreme low power operation. The communication framework relies on tag-to-tag backscattering with very limited energy resources. The computing framework relies on a novel AC computing methodology that facilitates local data processing with an order of magnitude less power consumption. These enabling technologies, as described in this paper, revitalize the concept of smart dust with significant impact on various application domains such as smart spaces, implantable devices, and environmental/structural monitoring.

A probabilistic approach is developed to evaluate the impact of power supply voltage fluctuations on the output error probability of tunnel field-effect transistor (TFET) based integrated circuits (ICs) operating at low supply voltages. The proposed model is used to better understand the error probability of synchronous digital circuits designed with 22 nm III-V heterojunction TFET technology. A comparative analysis with high performance 20 nm FinFET and 22 nm CMOS based circuits is also provided to illustrate the related tradeoffs among supply voltage, frequency, and error probability for these three technologies. This investigation is important for energy-efficient TFET based circuits where noise sensitivity is higher due to ultra low operating voltages.

Security is a significant challenge for a variety of emerging applications within pervasive computing such as the deployment of IoT devices at a massive scale. SIMON, a lightweight cryptographic algorithm, is a promising candidate for encryption in a resource-constrained environment. An ultra low power hardware implementation of a SIMON block cipher is developed in this paper. The theory of adiabatic switching is leveraged in a bit-serialized SIMON core with 32-bit plaintext and 64-bit key. The proposed hardware-level innovations enable 27.5X higher energy efficiency (kilobit per second per Watt) at the expense of 18% less throughput as compared to conventional implementations.

Correlation power analysis (CPA) attacks on the hardware implementation of cryptographic algorithms can retrieve the cipher key by analyzing the correlation between hypothesized keys and the power measurement of that crypto hardware. The existing CPA attacks and the countermeasures are mainly for two-dimensional (2D) integrated circuits (ICs). There is a lack of study on CPA in the context of three dimensional(3D) ICs. To fill in this gap, this work investigates the impact of a 3D power distribution network (PDN) on the efficiency of CPA mounted on a cryptographic module, which is in one of the 3D planes. The Pearson correlation coefficient is used as a metric to assess the impact of different PDN types, circuit loads, and switching activities of the neighboring planes on the CPA efficiency.

Charge-recycling based AC computing has recently been proposed to significantly increase energy efficiency in wirelessly powered devices. The power consumption is reduced by 1) eliminating the rectification and regulation stages of traditional DC computing and 2) recycling charge through AC computing. An alternative charge-recycling mechanism is proposed in this paper that does not require a phase shifter or peak detector, thereby reducing the overhead power consumption. Simulation results in 45 nm technology demonstrate that an additional 60% reduction in power consumption can be achieved while operating at the same frequency. As compared to the traditional case, power consumption is reduced by more than an order of magnitude.

The applicability of package-embedded spiral inductors to switching buck converters is demonstrated. In the first step, the design and characterization process of package-embedded spiral inductors is investigated via comprehensive full wave electromagnetic simulations, while considering a realistic, multi-layer flip-chip package. An interleaved multi-phase buck converter with an array of package-embedded spiral inductors is developed in the second step. The converter produces an output voltage of 0.9 V from 1.2 V input voltage while supplying a load current of 1 A. The flexibility of the package is exploited to obtain a relatively high inductance, enabling a reduced switching frequency. Lower switching frequency minimizes the dynamic loss, thereby increasing the power efficiency. According to the extracted results of the overall layout, power efficiency of approximately 89% is achieved with 3% output ripple voltage.

Monolithic three-dimensional (3D) integrated circuits (ICs) achieve ultra-high density device integration through fine-grained connectivity enabled by monolithic inter-tier vias (MIVs). In this paper, an open source standard cell library for design automation of large-scale transistor-level monolithic 3D ICs is proposed. A 128-point, highly parallelized FFT core with 330K cells is implemented with the proposed library. Power and timing characteristics of monolithic 3D ICs are quantified. The effect of signal integrity and routing congestion on timing characteristics is investigated. The primary clock tree characteristics of monolithic 3D ICs are also discussed. The proposed open source cell library facilitates future research on multiple aspects of monolithic 3D technology.

Closed-form expressions to estimate power supply noise due to the simultaneous switching of I/O drivers are revisited in this brief. It is shown that existing closed-form expressions share a common limitation and underestimate noise with up to 83% error in advanced nanoscale technologies with fast signal rise/fall times. This characteristic is investigated, both quantitatively and qualitatively. New closed-form expressions are developed for the signals with fast transition times. Results demonstrate that the proposed closed-form expressions exhibit an average error of 3.3% as compared with SPICE simulations, and enhance the accuracy of the existing expressions by up to 79.4%.

New hardware security threats are identified in emerging three-dimensional (3D) integrated circuits (ICs) and potential countermeasures are introduced. Trigger and payload mechanisms for future 3D hardware Trojans are predicted. Furthermore, a novel, network-on-chip based 3D obfuscation method is proposed to block the direct communication between two commercial dies in a 3D structure, thus thwarting reverse engineering attacks on the vertical dimension. Simulation results demonstrate that the proposed method effectively obfuscates the cross-plane communication by increasing the reverse engineering time by approximately 5x as compared to using direct through silicon via (TSV) connections. The proposed method consumes approximately one fifth the area and power of a typical network-on-chip designed in a 65 nm technology, exhibiting limited overhead.

Low swing/voltage clocking is a well-studied approach to reduce dynamic power consumption in clock networks. It is, however, challenging to maintain the same performance at scaled clock voltages due to timing degradation in the Enable paths that are required for clock gating, another highly popular method to reduce dynamic power. A useful skew methodology is proposed in this paper to increase the timing slack of the Enable paths when the clock network is operating at a lower swing voltage. The skew schedule is determined via linear programming. The methodology is evaluated on five largest IS-CAS'89 benchmark circuits. The results demonstrate an average 47% increase in the timing slack of the Enable path, thereby facilitating low swing operation without degrading performance.

A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed design targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 5% of the output voltage) and power density. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20 ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm2. These results outperform existing studies and demonstrate the applicability of the proposed regulator to portable SoCs.

Limited energy is a significant challenge for IoT devices since frequent battery replacement is not feasible. Various energy harvesting techniques have been previously proposed to alleviate this challenge. A new circuit design technique is developed in this paper to significantly enhance the power efficiency of existing wireless energy harvesting methods. Contrary to the traditional approach, the rectification and regulation blocks are eliminated and the harvested signal is directly used to power the IoT device by leveraging charge-recycling circuit theory. In addition to higher energy-efficiency, the proposed approach also reduces the form factor and therefore lowers the cost of an IoT device. The methodology is evaluated using a 45 nm CMOS technology, demonstrating approximately five times reduction in power consumption compared to the traditional approach.

A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS'89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.

Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily gated clock networks where a local clock tree exists between clock gating cells and registers. A methodology is proposed in this paper to efficiently achieve clock skew scheduling in circuits with gated clock networks. The methodology is implemented via both linear programming and constraint graph based approaches, and evaluated using the largest ISCAS'89 benchmark circuits with clock gating. The results demonstrate up to approximately 21% reduction in clock period while maintaining the power savings achieved by clock gating. A conventional design flow is used for the experiments, demonstrating the applicability of the proposed algorithms to automation.

Low swing clocking is a well known technique to reduce dynamic power consumption of a clock network. A novel static D flip-flop topology is proposed that can reliably operate with a low swing clock signal (down to 50% of the VDD) despite the full swing data and output signals. The proposed topology enables low swing signals within the entire clock network, thereby maximizing the power saved by low swing operation. The proposed flip-flop is compared with existing low swing flip-flops using a 45 nm technology node at a clock frequency of 1.5 GHz. The results demonstrate an average reduction of 38.1% and 44.4% in, respectively, power consumption and power-delay product. The sensitivity of each circuit to clock swing is investigated. The robustness of the proposed topology is also demonstrated by ensuring reliable operation at various process, voltage, and temperature corners.

In this paper, charge recovery logic is proposed as an alternative to traditional or near-threshold CMOS logic for high-performance systems where the power is wirelessly delivered, e.g. bio-implantable devices. This approach has two primary, complementary advantages in i) providing a wirelessly transmitted sine-wave as the power clock source to the charge recovery logic and ii) eliminating the AC/DC power stage required to provide a stable supply voltage needed in CMOS circuits. The paper presents solutions to the main obstacles of this method and shows simulation results of a simple logic load designed in Efficient Charge Recovery Logic (ECRL) as part of a wireless powered system. The designed wirelessly powered ECRL (coined WP-ECRL) system i) consumes 15.2 × less power than full-swing CMOS and ii) operates at higher frequencies than near-threshold CMOS. These comparative trends in power dissipation are for the computing circuit only, and do not include the bulky AC/DC stage that would be necessary for CMOS implementations. In terms of resilience, it is shown that logic functionality is preserved even when the coupling coefficient of the wireless link is decreased by 60% from the nominal value or when coils with very poor quality factor (down to Q = 0.1) are used.

Low swing TSV signaling is proposed for three-dimensional (3D) integrated circuits (ICs) to reduce dynamic power consumption. Novel level shifters are designed to lower the voltage swing before the TSV and to pull the voltage swing back to full rail at the far end of the TSV. Proposed level shifters operate with a single supply voltage, thereby reducing the overall cost. Critical TSV capacitance beyond which the proposed scheme saves dynamic power is determined. Up to 42% reduction in overall power is demonstrated with a voltage swing of 0.5 V, where the supply voltage is 1 V.

A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay product (PDP) for each level shifter is analyzed and compared. Worst-case corner analysis is performed for transient power, delay, and leakage power. The dependence of power and delay on input supply voltage level is also investigated for each topology. Simulation results demonstrate 43% and 36% reduction in, respectively, transient power and leakage power as compared to cross-coupled level shifter, while consuming 9.5% and 79.5% less physical area than, respectively, cross-coupled and bootstrapping techniques.

A low-swing clocking methodology is introduced to achieve low-power operation at 20nm FinFET technology. Low-swing clock trees are used in existing methodologies in order to decrease the dynamic power consumption in a trade-off for 3 issues: (1) the effect of leakage power consumption, which is becoming more dominant when the process scales sub-32nm; (2) the increase in insertion delay, resulting in a high clock skew; and (3) the difficulty in driving the existing DFF sinks with a low-swing clock signal without a timing violation. In this article, a FinFET-based low-swing clocking methodology is introduced to preserve the dynamic power savings of low-swing clocking while minimizing these three negative effects, facilitated through an efficient use of FinFET technology. At scaled performance constraints, the proposed methodology at 20nm FinFET leads to 42% total power savings (clock network+DFF) compared to a FinFET-based full-swing counterpart at the same frequency (3 GHz), thanks to the dynamic power savings of low-swing clocking and 3% power savings compared to a CMOS-based low-swing implementation running at the half frequency (1.5 GHz), thanks to the leakage power savings of FinFET technology.

An analysis flow is proposed to determine the significance of induced (switching) noise in analog circuits. The proposed flow is exemplified through two commonly used amplifier topologies. Specifically, input-referred switching noise is introduced as the first figure-of-merit and compared with the well-known equivalent input device noise through analytic expressions. The comparison is achieved as a function of multiple parameters that characterize switching noise in the time domain (modeled as a decaying sine wave), such as peak amplitude, period, oscillation frequency within each period, and damping coefficient. The analytic expressions used to obtain input-referred switching and device noise are verified with SPICE simulations. These expressions are utilized to develop dominance regions for both noise sources. Furthermore, time-domain switching noise amplitude (at the bulk node) at which the input device and switching noise magnitude are equal (in the frequency domain) is determined as the second figure-of-merit, providing guidelines for the signal isolation process. Reverse body biasing is also proposed to alleviate the effect of switching noise by weakening the bulk-to-input transfer function as opposed to reducing the switching noise amplitude at the bulk nodes. It is demonstrated that this method has a negligible effect on primary design objectives of the victim circuit while reducing the input-referred switching noise by up to 10 dB. As a case study, the proposed flow is applied to a potentiostat circuitry where input sensitivity is of primary importance.

In traditional decoupling capacitor topologies, power gating can significantly degrade the system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance associated with the power-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: 1) relatively low-resistance through silicon vias (TSVs) and 2) ability of TSVs to bypass plane-level power networks when delivering the power supply voltage. In the proposed topologies, decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, achieving up to 50% and 87% reduction in, respectively, rms power supply and power gating (in-rush current) noise at the expense of a moderate increase in physical area and peak power consumption.

The design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to develop equivalent electrical models for both via-first and via-last based power distribution networks. Based on these models, a valid design space has been developed where power supply noise is satisfied and physical area overhead is minimized. Under constant power supply noise, a via-last based power network occupies 7.5% less area. However, in addition to causing routing blockages, a via-last based power network exhibits high sensitivity to design parameters due to a high quality factor. Alternatively, a via-first based power network requires a large number of TSVs, but exhibits relatively more predictable behavior due to a lower quality factor (higher damping).

A methodology is proposed to characterize TSV induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using a 3D transmission line matrix (3D-TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type and placement of substrate contacts.

Two topologies are proposed at the physical level to achieve reliable power gating in through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs). The proposed lumped and distributed power gating topologies address the unique differences among distinct TSV fabrication methods such as via-first, via-middle, and via-last, while achieving, on average, 85% reduction in the leakage power. Related tradeoffs among power supply noise, power gating noise, physical area, and turn-on time are also investigated.

Three-dimensional (3-D) integration is a promising technology to alleviate the interconnect bottleneck by stacking multiple dies in a monolithic fashion. Both power dissipation and delay can be reduced by utilizing the third dimension where through silicon vias (TSVs) are used for vertical communication. Characteristics of switching noise that couples to a sensitive device due to a TSV are investigated in this paper. A model is developed to evaluate the noise performance of a TSV. Several noise isolation strategies are also discussed. Ignoring noise characteristics during the TSV placement process produces a poor 3-D circuit with high susceptibility to switching noise.

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of P/G noise on crosstalk is analyzed for different line lengths, line widths, and interconnect driver resistances. Considering the P/G noise, a shield line can degrade rather than enhance signal integrity due to increased P/G noise coupling on the victim line. A$2\pi$RLC interconnect model is used to investigate the effects of both coupling capacitance and mutual inductance on the crosstalk noise. Physical spacing and shield insertion are compared in terms of the coupling noise on the victim line for several technology nodes. Boundary conditions are also provided to determine the effective range of spacing and shield insertion in the presence of P/G noise. Additionally, the effects of technology scaling on P/G noise and shielding efficiency are discussed, and related design tradeoffs are addressed.

A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the interdependence between the setup and hold times, reducing the delay uncertainty caused by variations. An algorithm is proposed to determine the interdependent setup-hold pair of a register. A data path designed with the proposed setup-hold pair improves the overall tolerance to variations. The methodology is evaluated for several technologies to determine the overall reduction in delay uncertainty.

Current propagation within a lightly doped substrate is approximated with a half-ellipse to efficiently estimate substrate resistances. As opposed to existing work, the proposed model contains only one fitting parameter. Compact models are also developed to determine the isolation efficiency of several commonly used structures such as a guard ring and triple well. The accuracy of these models is verified by comparing the models with a commercial substrate extraction tool based on a boundary element method. These models are used to compare several isolation structures within an industrial mixed-signal circuit with a lightly doped substrate.

A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution network of an aggressor circuit are exploited to reduce the overall number of input ports before the substrate extraction process. Specifically, the substrate of an aggressor circuit is partitioned into voltage domains where each domain is represented by a single substrate contact. The remaining ports of the substrate within that domain are ignored to reduce the computational complexity. A linear time algorithm is developed to identify these voltage domains and generate an equivalent contact. A reduction of more than four orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 20% error in the peak-to-peak value of the substrate noise voltage.

Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of noise in the P/G network is analyzed for various line lengths, line widths, and interconnect driver resistances. A 2pi RLC model is used to investigate the effect of both coupling capacitance and mutual inductance on the crosstalk noise. For a range of shield lengths and widths, a shield line can degrade signal integrity by increasing the crosstalk noise on the victim line. Different physical spacing and shield insertion methods are compared for various parameters in terms of the coupling noise on the victim line for a 65 nm technology node.

A simple, yet physically intuitive macrolevel model is presented to identify the dominant substrate coupling mechanism at the early stages of the design process, while simultaneously considering multiple parameters. Furthermore, the sensitivity of substrate noise to these parameters is evaluated, demonstrating the nonmonotonic dependence of noise on rise time. The design implications of the proposed analysis are discussed, identifying the preferred noise reduction technique for a specific set of operating points.

A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifyingvoltage domainson the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.

The non-monotonic behavior of power/ground noise with respect to the rise time tr is investigated for an inductive power distribution network with a decoupling capacitor. A time domain solution is provided for the rise time that produces resonant behavior, thereby maximizing the power/ground noise. The sensitivity of the ground noise to the decoupling capacitance Q and parasitic inductance Lgis evaluated as a function of the rise time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for trles 2radic(LgCd). Alternatively, reducing the parasitic inductance Lgis shown to be effective for trges 2radic(LgCd).

A methodology is proposed to improve the efficiency of the substrate impedance extraction process for a large scale circuit by exploiting the circuit activity. Similarly biased regions of the substrate short-circuited by the ground network are identified to reduce the computational complexity of the extraction process. Each of these voltage domains is represented by a single equivalent input port to the substrate, merging the remaining ports within that domain. An algorithm is presented to determine these domains and generate an equivalent port for each domain. The parasitic impedance of the ground network is updated to maintain accuracy. A reduction of more than two orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 15% error in the rms value of the substrate noise voltage at the sense node.

A substrate biasing methodology is introduced based on modifying standard cells by inserting dedicated substrate contacts in those cells behaving as aggressive digital noise generators. These contacts are connected to a dedicated ground network. The proposed approach reduces two primary noise injection mechanisms: ground coupling and source/drain junction coupling. Limitations of the Kelvin biasing scheme are removed while achieving more than a 60% (9 dB) reduction in substrate noise at the cost of a 12% increase in area.

A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period