status: Published

A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by >14 dB within the 1st Nyquist zone, and >8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within$1\times 10 ^{5}$iterations.

This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and low- area ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2nd-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PWM waveform define only two operating points of the VCO, therefore guaranteeing linearity. In addition, the phase quantization error between two consecutive samples is generated by a phase detector and processed by a second VCO. Together with the output of the first VCO, a MASH 1-1 2nd-order noise-shaping VCO-based time-domain delta-sigma converter is obtained. Fabricated in 90 nm CMOS technology, the SFDR is larger than 67 dB without any calibration for a 20 MHz bandwidth.

This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB EVM and 18% efficiency. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The amplitude modulator has a segmented architecture. This results in a very compact 0.007 mm2chip area.

A wide tuning range LO generation architecture for software defined radio is presented. A dual VCO approach followed by a programmable divider chain based on high-speed dynamic CMOS latches provides full rail-to-rail operation with low power consumption. The 1.2V 90nm CMOS implementation achieves a VCO tuning range between 6 to 13.6GHz for a power consumption between 3.5 to 13.4mW and phase noise figure of merit of 182dBc/Hz measured at 3MHz offset from a 12GHz carrier. The VCO-multiplexer and divider chain consumes between 5.9 to 8.1mW for this frequency range.

This paper presents a digital amplitude modulator (DAM) for polar transmitter in 90 nm CMOS technology. It consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. To reduce the aliases due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achieving -26.1 dB error vector magnitudes (EVM) and 18% drain efficiency. The 8-bit are segmented addressed. This results in a very compact 0.007 mm2chip area.

This paper presents a design methodology for fully reconfigurable low-voltage Delta-Sigma converters as for instance used in next-generation wireless applications. The design methodology first finds the power-optimized noise transfer functions for the different standards at system level and then translates them into optimal granularities of programmability and circuit parameters such as resistance and capacitance values for the integrators. Reconfiguration is done in the passive component arrays, modulator orders, number of quantizer bits and transconductance for optimal power consumption. This gives the design the best trade-off between power and performance for every configuration mode.

In digital phase-locked loop based fractional-N RF frequency synthesizers, the use of a Time-to-digital converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of SigmaDelta-noise cancellation on the fractional spurs.

Software defined radio (SDR) transceivers comprising a single highly reconfigurable circuit have proven to enable multi-mode multi-band operation at low-cost. However, distortion induced by circuit imperfections hampers standard compliancy over the diverse modes and bands. In this paper, a solution is presented and implemented in hardware to eliminate this distortion by using digital in-system calibration. The proposed calibration scheme offers system performance improvements beyond standard compliancy, achieving e.g. an error vector magnitude (EVM) of 1.8%, a quadrature imbalance of -46 dBc and -42 dBc at the transmitter and receiver output respectively and a carrier feedthrough of -38 dBc. This calibration scheme is very efficient and directly applicable on most SDR transceivers, even in a multiple antenna (MIMO) configuration.

A digital in-system calibration method is presented eliminating distortions caused by transceiver circuit imperfections such as quadrature imbalance, carrier feedthrough and receiver DC-offset. The method enables standard compliancy over multiple modes and multiple bands while using a low-cost Software Defined Radio (SDR). By using non-iterative algorithms and standard compliant calibration signals, the system remains operational during calibration. As the calibration does not require dedicated circuitry, there is no penalty in area or design effort and is thus applicable on most SDR. Implementation shows Error Vector Magnitude (EVM) performance improvements down to 1.8%.

A baseband filter synthesizer that takes a behavioural description of the design and produces an efficient transistor level implementation is presented. The tool optimizes the filter at the cascade level, providing the best trade-off between power consumption and dynamic range, and at the cell level, selecting minimum power solutions, through accurate analytical models and an efficient bi-quad topology. Differently from past cascade design techniques based on dynamic range optimization through linear programming, we focus on power minimization while guaranteeing minimum performance levels, given the increasing importance of power savings in hand-held devices. A synthesized filter has been realized in silicon demonstrating the effectiveness of our approach

The 4th generation of wireless systems needs low-power integrated transceivers that can be reconfigured in order to satisfy different standard requirements. Standard analog blocks are often not suitable for this step towards the future because of their lack of flexibility. We defined a novel approach to make active-Gm-RC biquadratic cells completely reconfigurable. The biquad provides digitally programmable bandwidth and hence power consumption with a fully customizable cut-off frequencies range. Besides, the noise level can be conveniently modified leading to a further power saving. We exemplified the use of this basic building block in the design of a flexible low-pass filter for a zero-IF transceiver. A 2nd/4th/6th order Butterworth filter was implemented with a continuous cut-off frequency tuning between 330 KHz and 24.6 MHz and with a current consumption range between 0.6mA to 26mA

Fourth-generation wireless communication systems (4G) will have totally different requirements than what front-end designers have been coping with up to now. Designs must be targeted to multi-mode and reconfigurability, leading to the concept of a software-defined radio. A large part of such a radio will be integrated into a complex SoC, where the substrate noise coupling problem must be solved.However, for an optimal implementation of the complete system, including e.g. PA, RF filters and antenna, different technologies must be combined in a single package, merging the worlds of microwave 's-parameter' designers and IC 'spice' designers. Design and simulation environments efficiently combining the assets of both are needed.At the same time, optimized mixed-signal radio architectures including digital compensation techniques that overcome the limitations and inaccuracies of the analog front-end must be developed. Again, efficiently designing and simulating such mixed analog/digital architectures requires an optimized tool capable of combining RF simulation techniques with digital system model simulation.