Demo Data from EDBT 2026 / reviewers in the wild / expert
Albert V. Ferris-Prabhu
dblp:48/2939
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Hardware reliability and fault tolerance · 50% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › design for manufacturability
yield modeling |
0.0 | 1 | 1992 | On the assumptions contained in semiconductor yield models · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Methods — techniques the papers use, named apart from their topics
scaling rules · 0.0poisson model · 0.0compound poisson model · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | On the assumptions contained in semiconductor yield modelsabstractIt is shown that the form of semiconductor yield models, and their predictions, are to a large extent affected by the size distribution of all defects and the spatial distribution of fatal defects. As the effects of these and other assumptions on yield models are rarely described in the literature, the author examines them and develops scaling rules for the average number of fatal defects per chip. To trace differences in the predicted yield to the various assumptions, the treatment compares a simple Poisson model with a compound Poisson model and shows that, when appropriate scaling rules are used, yield predictions of the simple Poisson model are accurate for a new product with chips with areas up to an order of magnitude larger than chips of existing products.> Albert V. Ferris-Prabhu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |