The autoregressive nature of Large Language Models (LLMs) has enabled remarkable performance in language generation, making them a cornerstone in natural language processing. As context windows lengthen, the per-token key–value (KV) cache grows linearly with sequence length and turns the generation stage into a memory-bound operation. However, existing works focus primarily on an isolated stage of KV cache reduction, and most efforts incur significant hardware overheads. This results in a lack of cross-stage co-optimization and leaves significant reduction potential untapped. To address these challenges, we propose CrossKV, a software-hardware co-design architecture that accelerates LLM inference to fully achieve the potential of KV caching optimization. Motivated by our observation, we identify the three stages in KV caching and present a cross-stage co-optimization algorithm, including: a derivative-enhanced dynamic progressive pruning method, a DCT-driven key-vector low-rank compressing, and a dynamic clustered hybrid run-length encoding to reduce the KV caching while maintaining high accuracy. Then, an efficient architecture featuring cross-stage dynamic co-optimization with negligible hardware overhead is proposed to fully harness the algorithm of CrossKV. Our evaluations of CrossKV over 9 popular LLMs models and various long-context tasks demonstrate an average of$6.03\times $and$4.10\times $improvement for energy efficiency and speedup compared to existing SoTA Accelerators architecture. Compared to the Nvidia A100 GPU, CrossKV achieves an average$23.43\times $energy efficiency and$4.64\times $speedup, respectively.

This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.

With the increasing demand for large-scale model deployment, cloud-based computing remains indispensable. However, energy and bandwidth overheads in edge-to-cloud data transmission pose significant challenges. This work presents a low-power, multimodal SoC that performs on-chip image and audio compression processing, enabling energy-efficient and low-latency cloud interaction for Internet of Things (IoT) applications. The SoC employs a two-level optimization strategy. At the microarchitecture level, a customized 16-bit fixed-length complex instruction set computing (CISC) microprocessor is introduced. Validated against a RISC-V minimal baseline RV32E equipped with equivalent peripheral engines, the proposed core achieves a$5.06\times $reduction in core logic gate count and up to$2.42\times $improvement in energy efficiency under iso-latency conditions. Additionally, a multipower domain strategy is adopted to further optimize energy efficiency, yielding$5.03\times $and$4.13\times $improvements for image and audio modes, respectively. Fabricated in a 65-nm CMOS process, our SoC integrates both image and audio processing, achieving an ultralow power consumption of 54.1–$387.5~\mu $W. It outperforms state-of-the-art dual-modal processors, achieving a$2.84\times $reduction in image-processing core power and a$12.78\times $reduction in audio compression power. Furthermore, our SoC achieves an energy efficiency of 206 pJ/bit of audio task and 15.5 pJ/pixel of image task, which offers a scalable and energy-efficient solution for versatile IoT deployments.

This paper proposes a sample-and-hold amplifier (SHA)-less front-end stage structure suitable for pipeline ADCs in time-interleaving architecture with large interleaving factor. A low resolution SARADC is adopted as the sub-quantizer, and a bridge capacitor is introduced to connect the two capacitor arrays of the MDAC and the sub-ADC. Compared to commonly used pipelined-SAR ADC architectures, the proposed front-end stage structure reduces the reference load on the sub-quantizer during coarse conversion, while preserving the benefits of a shared sampling network in the sampling process. A 14-bit 500-MS/s pipeline ADC channel in an 8-way time-interleaved architecture utilizing the proposed front-end stage structure is designed in 28-nm CMOS process. Simulation results well demonstrate that the proposed front-end stage structure is highly immune to aperture errors, and shows the ADC channel achieves 69.13 dB SNDR and 83.8 dB SFDR at Nyquist frequency. With an estimated power consumption of 40-mW, a Walden FoM of 34.24-fJ/conv.-step is achieved.

This paper presents a PVT-robust, high gain range and high linearity analog baseband (ABB) circuit for wideband communication. The ABB circuit consists of a four-stage programmable gain amplifier (PGA) and an embedded second-order low pass filter (LPF). In order to satisfy the PVT variations, a novel PGA topology based on two-stage miller OTA with self PVT compensation and dynamic pole-capturing technique is proposed. Besides, the ABB circuit uses floating-bulk bias method to achieve high linearity. Fabricated in 28-nm CMOS process, the measurement results show that the ABB circuit can provide a programmable gain range from 0 to 40 dB with 6 dB coarse and 1 dB fine step, while the 3 dB bandwidth greater than 550 MHz. It obtains an OP1dBof 5dBm and OIP3 of 26.1dBm for the maximum gain state. The ABB circuit occupies a core area of 0.23 mm2and consumes a DC power consumption of 15 mW from 0.9-V supply.

This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.

A flipped voltage follower (FVF)-based capacitor-less low-dropout (LDO) regulator is presented that features a fast transient response. The adaptive zero compensation is proposed to solve the full-load-range stability issue associated with the FVF LDO regulator. The presented FVF LDO regulator has been implemented in a 0.18 μm CMOS process with an active area of 0.026 mm2. The simulated loop phase margin exceeds 45° for the entire load range of 0-40 mA. The minimum power supply rejection of 56 dB at 1 MHz has been measured at the maximum load current of 40 mA. The measured transient response time is 0.48 ns over the load current range with a dynamic quiescent current of 36 to 76 μA, which results in a figure of merit among the best reported in recent publications.

A Q-learning based current-steering digital to analog converter (DAC) calibration method is proposed in this paper for spurious-free dynamic range (SFDR) improvement. A look-up table (LUT) to control the switching sequence of the DAC elements is achieved by Q-learning for an optimal SFDR. Compared with the fixed element transition strategy proposed by manual derivation, the LUT can be updated by off-line training to deal with diverse and complex non-ideal factors limiting the SFDR of DAC. In this paper, a 2.0-GS/s 12-bit segmented current-steering DAC in 28nm process is simulated and the equivalent model is extracted to verify the effectiveness of the method. Simulation results show that, the SFDR over entire Nyquist bandwidth is larger than 70 dB with about 8 dB improvement using the proposed Q-learning method.

A resource-efficient neural-network-based face detector using 1.5-bit frame-to-frame delta quantization with diagonal spatial feature extraction method is proposed in this paper, which is designed for resource-limited always-on camera sensors. The proposed architecture completes analog-domain frame difference for motion sensing, which triggers digital-domain feature extraction. Based on the sparse and effective features, a lightweight convolutional neural network is devised as a classifier. A self-recorded dataset of 313 videos for humans of different appearances, light intensity and backgrounds is used to validate the performance of the proposed method. Simulation results show that the proposed method achieves 93.6% accuracy using only a$\boldsymbol{50\times 50}$pixel array, which is higher than the prior discontinuous temporal change quantization method. Meanwhile, the conservatively estimated power consumption of the proposed method can be reduced by$\mathbf{14 \times}$compared to the state-of-the-art work.

Human bowel sounds (BSs) contain rich information on gastrointestinal health status. Recently, the wearable BS monitoring systems has made it possible to record the human BSs in the long term. However, BSs collected by long-term monitoring devices usually contain various types of noises, which significantly affect the detection accuracy on BS events of interest. To filter out the noises in the long-term BS recordings, a U-Net convolutional neural network (CNN) based BS quality enhancement algorithm is proposed. The algorithm features a frequency-domain BS enhancement using U-Net to efficiently suppress the amplitude spectrum noises of BS segments. Experimental results on our BS dataset show that after enhancing with the proposed algorithm, the average SNR improvement of the sound segments is 28.72dB, which is the best among similar works. Moreover, after the enhancement, the accuracy of BS event detection using a threshold-based approach can reach 98.38%, which proves the effectiveness of the proposed enhancement algorithm. To the best of our knowledge, we are the first to utilize the CNN for BS quality enhancement.

A Ternary neural network (TNN) based patient- specific single lead Electrocardiography (ECG) processor for the early detection of cardiac arrhythmias (CA) is presented. The designed system detects upward/downward turning points in the ECG to detect the slope variation and calculates the fiducial points of the PQRST beats, with high auto-patient adaptability. A 3-layer Feedforward Neural Network with ternary weights is integrated on the sensor to classify eight different types of Shockable CA (SCA) and non-SCA (NSCA) with sensitivity and specificity of 99.1% and 99.8% respectively. The proposed processor is also synthesized using 65nm CMOS technology having an area of 1.08 mm2with an overall power consumption of 2.52 μA, energy efficiency of 72 nJ/detection.

This paper presents a 915MHz band ultra-low-power receiver with high energy efficiency for IoT applications. With the proposed polar receiver topology, the received Star- 16QAM signal is split into an ASK signal and D8PSK signal. A phase-tracking loop working as a phase domain ADC is adopted to demodulate the D8PSK signal, while the ASK signal can be demodulated by using a mixer-based energy detector chain. The receiver was designed and simulated in 65nm CMOS technology. Under 1V supply voltage, the power consumption of 445 μ W and the energy efficiency of 110pJ/bit have been achieved, which is at least 3.5× and 7.1 × better than prior arts, respectively. The simulated sensitivity is -76dBm at a data rate of 4Mbps. The figure of merit (FoM) of the receiver is 176dB.

An analog-intensive voice feature extraction method based on time-domain filtering is proposed in this paper, which solves the computational complexity problem in Mel Frequency Cepstral Coefficient (MFCC) extraction. Compared with MFCCs, the estimated power consumption of the proposed feature extraction is reduced by approximately 4×. Besides, a binarized neural network model called DSXNOR-Net with low parameters is proposed together with the generalized end-to- end (GE2E) loss function for speaker verification. The feature extraction method and DSXNOR-Net are verified by Python. The proposed architecture achieves an optimal recognition accuracy of 98.3% on an English spoken digits corpus for keyword spotting (KWS) and 94.4% on TIMIT corpus for speaker verification (SV). The total estimated power consumption is reduced by approximately 2X and 4X for SV and KWS compared to the state-of-the-art results.

Motivated by the ultra-low power design demands of the integrated implantable medical electronics and systems, a switched-capacitor DC-DC converter is presented in this paper. The DC-DC converter is controlled by hysteretic control approach, which has inherently stable and fast loop speed compared with the approach using error amplifier. To achieve higher power efficiency and lower quiscent current, in addition to optimizing the switching frequency and width of the core module of the converter, Low power design methodes are used for the functional module. By operating transistors in the subthreshold region and decreasing operating frequency, the short current and dynamic power can reduce a lot. The converter has designed in 0.18μm standard CMOS technology. It can achieve step down voltage conversion of 1.2V with a ripple voltage of 1.4mV from 2.5V input voltage. A high power efficiency of 88.3% can be achieved at a load current of 3μA. It also produces about 34nA low quiescent current without load, which is suitable for the integrated implantable biomedical electronics.

Impedance matching plays an important role in radio frequency circuits. To achieve dynamic load modulation in back-off operation for power amplifier or address the variation of antenna impedance due to complicated environment, tunable matching networks are demanded. To optimally design the coverage area within the Smith Chart for common ladder networks, analytic calculating procedure and computer optimization method has been proposed. The calculating procedure can be applied to arbitrary ladder networks and the optimization algorithm can acquire the optimal network automatically with appropriate constraints.

This paper presents a fully-integrated 8 MHz relaxation oscillator for ultra-low-power applications. Fabricated in 0.13 μm CMOS process, the oscillator occupies an area of 0.022 mm2. With adaptive reference generation and low-swing oscillation design, the power consumption is 2.8 μW, resulting a figure-of-merit of 0.35 nW/kHz. The adaptive reference feedback compensates the comparator delay and filters out the low-offset frequency part of the noise and temperature variation. To reduce the frequency influence due to current mismatch on the reference voltage and oscillation node, cascode current mirrors are applied. To reduce the influence due to the delay of capacitor reset logic, a pulse-to-edge generation block is used. The measured temperature stability is 1.24% in the temperature range of -20 °C to 60 °C and the measured periodic rms jitter is 180 ps, 0.144 % jitter-per-period on the output.

Human bowel sounds (BSs) deliver much useful information about gastrointestinal health status. In recent years, the utilization of advanced bio-acoustic sensors, such as the wired electronic stethoscopes and the wireless wearable sound recording patches, has enabled researchers to record, store and analyze the BSs in digitized manners, i.e., computerized bowel sound analysis. However, for collected BS recordings, how to effectively pick up the segments that contain BS events while ignoring those segments that only contain background noises remains difficult. Moreover, the BS segment recognition algorithms that are meant to be applied in the wearable healthcare scenes are further required to retain a low computation complexity. In this work, a light weighted BS recognizer based on convolutional neural networks (CNNs) is proposed for wearable systems. Specifically, the proposed recognizer firstly converts each one-dimensional segment into a two-dimensional spectrogram by calculating the Mel-frequency cepstrum coefficients (MFCCs) frame by frame and then passes the spectrogram through a CNN to infer the category of the segment. To validate the CNN-based BS recognizer, a 28 minutes of BS dataset that contains 955 BS-present segments and 725 BS-absent segments are made. Experimental results on the dataset show that the recognizer attains the 91.25% and 90.83% mean accuracies for the `not-across-subjects' and `across-subjects' validation, respectively. Moreover, compared with the state-of-the-art LSTM approach, the CNN-based BS recognizer is light-weighted with only 20.35k parameters, which is a quarter of that of the LSTM. Due to the lower model complexity, the CNN-based BS recognizer has the potential to be integrated into the gateways in a wearable system to secure the function that only the BS-present segments are allowed to be relayed to the remote. User privacy can be better protected in this way.

This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is proposed for the flash sub-ADC-based pipeline ADC to reduce the aperture error, and expand the ADC input frequency up to 490 MHz under 200-Ms/s sampling rate. To further improve the accuracy and reduce power, the sampling capacitor splitting and comparator interpolation techniques are used in the first stage. The proposed ADC has been designed and fabricated in a 180-nm CMOS technology with an area of 2.43 mm2including ADC core, the biasing, and the calibration circuit. The measured signal to noise and distortion ratio (SNDR) is 70.6 and 65.6 dB for 30- and 385-MHz inputs, respectively. The SNDR remains 63.1 dB for 490-MHz input. The ADC core consumes 112-mW power under 1.8-V supply. The measured effective resolution bandwidth (ERBW) is about 250 MHz, and the Walden figure of merit (FoM) defined at the ERBW is 116 fJ/conversion-step.

A wearable ECG monitoring device with accelerometer aided activity recognition is proposed in this work. A 3-axis accelerometer is integrated in the Band-Aid alike wearable device which will be stuck to the user's chest. The Lead V2 ECG signal and the chest acceleration data are recorded synchronously. An activity recognition algorithm is proposed to identify certain types of daily activities, including coughing, walking, standing, sitting, squatting or lying based on the chest acceleration data. The recognition result can be further used to correlate the recorded ECG signal to the user's activity. Experiments on 13 volunteers with age of 5 to 68 show that the proposed algorithm have an overall accuracy of 96.92%. The recognition result can be further used to correlate the recorded ECG signal to the user's activities.

An integrated 21.4-22.4 GHz fractional-N phase-locked loop (PLL)-based frequency synthesizer with low phase noise LC voltage-controlled oscillator (VCO) is implemented for a RF receiver in wireless communication systems. The K-band VCO generates a signal with a phase noise that is lower than -93.4 dBc/Hz at 1 MHz offset frequency, using a current source filtering technique to improve the phase noise while having a 11% tuning range. The VCO achieves a figure-of-merit (FOM) of -179.5 dBc/Hz with a power consumption of 16 mW. The transient mismatch of the charging and discharging current in the charge pump is optimized about 0.1% in the typical case, which minimizes the steady-state phase error in the PLL. The PLL outputs a signal with a phase noise that is lower than -97.5 dBc/Hz at 1 MHz offset frequency with a total power consumption of 53 mW in 90 nm CMOS.

A 4-bit 4Msps successive approximation (SAR) phase-domain analog-to-digital converter (Ph-ADC) for zero intermediate frequency (IF) Bluetooth low energy (BLE) receivers is proposed. With the SAR operation, the Ph-ADC requires only 52 current elements and 1 comparator, in contrast to the conventional design which needs 260 current elements and 8 comparators. Simulation results show that the digital intensive Ph-ADC consumes only 7.9μA current from a 1.8V supply when implemented in a 180nm CMOS process.

An energy-efficiency 16-QAM/MSK transmitter (TX) working at 432 MHz is presented for the short range communications. By adopting the edge-combining power amplifier (ECPA), only an injection-locked ringing oscillator (ILRO) with very low frequency is required, in comparison to the high frequency local oscillator in conventional TX's, which helps to reduce the power consumption of this TX significantly. A new method to control the amplitude of the edge-combined quadrature signals is proposed to generate the 16-quadrature amplitude modulation (16-QAM) and minimum shift keying (MSK) modulations in this work. A finite impulse response (FIR) filter is introduced in the ECPA for side lobe suppression enhancement. Implemented in a 0.18 μm CMOS process, the proposed TX consumes 468 μW when outputting -15 dBm 50 Mbps 16-QAM/MSK signals in simulation. Under 1 V supply, the TX can achieve an energy efficiency of 9.4 pJ/bit at the maximum data rate of 50 Mbps. The phase noise of the RF output in the injection-locked state is -103 dBc/Hz, at 1MHz offset.

A fractional-N frequency divider based on a 5-bit phase interpolator (PI) is presented in this paper. A novel PI unit cell with the switched resistor loads is proposed to break the constraint brought by the variation of the common-mode output voltage, providing an extra design degree of freedom for the optimization. An all-digital phase rotating scheme is proposed to achieve an excellent balance between the robustness of the phase interpolation and the speed limitation of the synthesized phase control circuit. The proposed fractional-N frequency divider is designed in 65-nm CMOS technology, dissipating 1.13-1.3 mW from a 1.2-V supply with the quadrature input signals at 2.4 GHz. To further evaluate the influence of the PI non-linearity, a behavioral simulation model based on Simulink is built. The behavioral simulation results show that the in-band spur induced by the fractional-N frequency divider is -51.8 dBc.

This paper presents an ultra-low voltage and ultra-low power PVT tolerant digital PLL with a semi-digital low dropout regulator (LDO). A low cost integrated temperature compensation circuit (TCC) is proposed and implemented by combining with a proposed ΔΣ LDO to reduce temperature variation of the digitally-controlled relaxation oscillator (DCRXO). A 50-to-145MHz PLL implemented in 65nm CMOS consumes a 77.3μW from a 0.6V supply at 100MHz output and achieves the phase noise of -94.3dBc/Hz at 1MHz offset frequency and the reference spur below -70dBc at 6.25MHz offset frequency. The output frequency variation of open-loop oscillator with the TCC is less than 5% across temperature variation from -20°C to 90°C.

A single-inductor dual-output (SIDO) buck converter with adaptive freewheel current and hybrid mode control is presented in this paper. It operates in pseudo-continuous conduction mode (PCCM) with single freewheel phase to reduce switching loss and minimize cross regulation. Freewheel current adjustment is implemented by detecting and control freewheel time, which can extend the load range and improve efficiency. For unbalanced load, this paper further proposed a hybrid PWM/hysteretic mode control scheme, which enables the two sub-converters to work at their own mode based on the load, independently of each other. The converter was designed with a 0.18μm CMOS process. Simulation results show that the efficiency reaches 87% in PWM mode. At light load, it is still higher than 80%.

This paper presents a fast mixed-signal automatic gain control (AGC) method for zero-IF/sliding-IF receivers used in wireless personal and body-area networks (WPAN/BAN). The preamble defined in Bluetooth low energy (BLE)/802.15.4 /802.15.6 specifications are as low as 1 Byte. It is a tough challenge for the zero-IF/sliding-IF receivers to perform AGC training, frequency synchronization and symbol timing estimation. By detecting the RF input of the quadrature mixer, IF input of analog filter and ADC output, the proposed method can achieve a desired IF amplitude within 1 bit when interference signal is small and 3 bits when carrier-to-interference ratio (CIR) is -27dB.

The fetal heart rate is vital for monitoring fetal well-being. Fetal heart rate monitoring based on acoustic techniques is passive and noninvasive. In this work, a fetal heart rate monitoring system based on phonocardiographic method is proposed. A portable low-power stethoscope is customized which meets the need for sensitivity in the monitoring. A noise cancellation method and adaptive matching method are applied to extract the fetal heart rate effectively. Clinical trials are carried out on pregnant women, and the comparison of fetal heart rates given by the proposed system with those given by the Doppler monitor is given to show the accuracy.

This paper presents a novel DC offset calibration method for the zero-IF (intermediate frequency) receiver that removes the PGA-gain-correlated offset residue. The conventional calibration method is usually based on the classic input/output referred offset model, in which the receiver IF programmable gain amplifiers (PGAs) have offset sources that varies a lot with different gain settings. Consequently, the conventional calibration method needs to generate the calibration code at each gain step and requires a huge look up table (LUT) to store the calibration values. This paper presents a new DC offset model which is gain non-correlated, by analyzing two types of commonly-used PGA. Based on the new model, a LUT-free single-step DC offset calibration method in together with the implementation circuit is designed. The proposed method has been verified on a practical zero-IF receiver circuit in a standard 0.18 μm CMOS technology through the Monte Carlo (MC) simulation. The simulation results show that the receiver IF output offset residue after calibration using the proposed method is reduced to below 12 mV, which is comparable to the LUT-based conventional calibration.

This paper presents an energy-efficient implementation of a real-time on-demand MAC protocol for medical wireless body sensor network (WBSN). Medical WBSN is focused on pervasive healthcare and medical applications, such as monitoring vital signs, making basic drug delivery, etc. The sensor nodes in the heterogeneous WBSN generally require different data rates, due to their differing functions. Additionally, because of the strict resource constraints, the sensor nodes must be ultra-low-power. Thirdly, low-rate treatment-function nodes must also ldquowork-on-demandrdquo to prove proper activities in the slave nodes such as stimulus and drug delivery. These three requirements cannot currently be satisfied simultaneously in commonly-used single channel implementations because the channel monitoring consumes too much power for long-term use. In the proposed implementation, a secondary channel is introduced in, which is used for channel listening only. Benefiting from the secondary channel, the node can achieve both real-time ldquowork-on-demandrdquo and zero idle power, by means of recovering energy from the ldquodemand tokenrdquo. An elaborated energy-harvesting RF module achieves monitoring the secondary channel. The prototype system of sensor nodes is expected for the zero-idle-power and the response time of less than 2 ms.

A rigorous and complete analysis of the deterministic DEM (DDEM) DAC performance is presented. With this analysis, DDEM DAC's equivalent linearity as ADC static linearity test stimulus source can be precisely predicted. Simulation result is given to validate this theoretical analysis.

Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. Onchip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs’ nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLkerror of 12-bit ADCs to ±0.2LSB accuracy level using only 7-bit linear DACs.

This work presents a deterministic dynamic element matching (DDEM) approach which is applied to low precision DACs to generate stimulus signals for ADC testing. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance of an 8-bit DDEM DAC (linearity less than 5 bits without DDEM) is comparable to or better than the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test(BIST) environments.