Voltage-controlled oscillator (VCO)-based comparators offer higher energy efficiency as the difference in input magnitudes increase, such as in level-crossing ADCs. Nevertheless, to date, they require a clock signal to perform comparison operations. This is incongruous with continuous-time applications, where inputs are compared continuously. Further, they lack hysteresis, a crucial feature for mitigating spurious switching that compromises energy efficiency. In this paper, we present a novel VCO-based comparator that, for the first time, simultaneously achieves continuous-time operation and high energy efficiency. The former feature is enabled by a novel continuous-time decision circuit, while the latter is achieved through a novel switched-current hysteresis circuit that mitigates spurious switching. The proposed comparator is designed in 65 nm CMOS. Simulation results show that it achieves low energy per comparison, ranging from 0.07 to 4 pJ, with an average propagation delay of ~15 ns. The average energy consumption is 0.19 pJ — ~1.8× lower than the state-of-the-art VCO-based comparator.

This paper presents a novel digital inductor-current estimator for digitally-controlled current-ripple-based synchronous DC-DC buck converters. The estimator features high accuracy, which is imperative for current-ripple control that requires precise estimation of instantaneous DC and inductor ripple currents in both the discontinuous and continuous conduction modes. The estimation method indirectly determines the currents by constructing a digital representation of the voltage across the inductor, rendering it applicable in both conduction modes. This method is more accurate and simpler than conventional methods that estimate DC and inductor ripple currents directly in each conduction mode. Compared to state-of-the-art methods, the proposed estimator achieves an average DC current estimation error that is ≥5.7× smaller and an inductor ripple current estimation error that is ≤ 1.90% over various load conditions.

The passive devices in state-of-the-art miniaturized switched-mode DC-DC converters are generally integrated by means of on-chip and in-package methods. Nevertheless, the quality is poor-to-moderate, thereby compromising the power-efficiency. In this paper, we propose the miniaturization of the DC-DC converter by means of realizing its passive devices as embedded devices that are printed within a high-density 3D inkjet printed-circuit-board (PCB). We propose a fourth-order stacked LC filter embodying passive components with small values-effectively at no additional cost because they are embedded through 3D-printing. For the inductor and capacitor, we propose to adopt a high-$Q$solenoidal structure and the metal-insulator-metal planar structure, respectively. The proposed filter is printed within the 3D-PCB with a compact 124 mm3volume due to the stacked arrangement. The measured AC attenuation is 21.2 dB at 200 MHz. The filter is further verified by means of computer simulations of a DC-DC buck converter. Simulation results of the converter employing the filter show a low output voltage ripple at 146 mV and a high peak power-efficiency of ~78% at 200 MHz switching frequency with 150 mA load current.

This paper presents a digital current sensor for digitally-controlled current-ripple-based DC-DC buck converters to estimate the instantaneous inductor-current ripple accurately in both the Discontinuous (DCM) and Continuous (CCM) Current Modes. The current sensor employs a proposed dual-mode input multiplexing technique to select an appropriate representation of the pertinent voltage of the switching node$(\boldsymbol{V}_{\boldsymbol{x}})$in any mode, thereby allowing the current to be estimated more accurately compared to that of the prior-art design. The accurate inductor-current ripple information enables the controller to yield output-voltage transient response with small overshoot or undershoot (OS/US) and fast settling time. Benchmarking results using a digitally-controlled current-ripple constant on-time DC-DC buck converter show that the converter employing the proposed sensor achieves$\geq \mathbf{49}{\%}$smaller OS/US and$\geq \mathbf{45}{\%}$faster settling time at the output voltage in both the DCM and the CCM collectively compared with that of the same converter but with the prior-art sensor.

The average power-efficiency of integrated DC- DC converters for Internet-of-Things is generally compromised over a wide load current range. This is because their efficiency is typically severely compromised at light load currents. We present a novel asymmetrical segmented power-stage configuration to improve the average power-efficiency of integrated converters. We achieve this by configuring different power-stage segments with different sizes of power transistors and their inductors, and a circuit to enable the corresponding segment for high power-efficiencies at different load conditions. Specifically, the circuit enables the segment with small-sized power transistors and a large inductor for light-load operations, and conversely, it enables the segment with large-sized power transistors and a small inductor for heavy-load operations. The integrated converter employing our proposed configuration is designed using a CMOS 180 nm process for 2. 5-3.3V input, 1.2 V output, and 50 MHz switching frequency. Simulation results show the proposed converter achieves a high average power-efficiency at ~73% over a wide load current range of 5-200mA. When benchmarked against the competing contemporary designs, the proposed converter features 5-30% higher average power-efficiency over the wide load current range, and >34% higher power-efficiency at 20 mA light load.

Planar air-core inductors come in a variety of geometrical shapes, including in the form of the conventional spiral geometry and novel complex geometries. In the design phase of a system, the inductance of the employed inductor would need to be ascertained. This is usually ascertained by tedious mathematical derivations on a segment-by-segment (inductor) basis or time-consuming computer modeling, and the complexity can become intractable for complex geometries. In this paper, we propose a versatile, yet accurate, vector-based method to ascertain the inductance of planar air-core inductors with virtually any geometry, including novel complex geometry inductors—rather easily. Our proposed method decomposes the inductor segments into vectors, and thereafter utilizes geometric models to compute the inductance in a systematic fashion. We benchmark our proposed method against the conventional electromagnetic field solver simulations to estimate the inductances of six planar inductors ranging from a conventional spiral air-core inductor to that embodying different and complex geometries. On the basis of these six inductor examples, we show that our method is highly accurate with a worst-case error of $\sim 5$% compared to that obtained using conventional electromagnetic field solver. Of particular interest, our modeling for novel complex geometry planar inductors is relatively simple.

Power-loss analyses for conventional (non fully-integrated) switched-mode dc-dc converters (SMCs) in the literature ignore the power losses due to the inductor and the gate driver of the power transistor. These losses are no longer negligible in fully-integrated SMCs. We propose closed-form expressions that characterize the aforesaid losses in fully-integrated buck SMCs. Using the expressions, we further analyze the overall power-efficiency, and show that designers can quickly find the combinations of design parameters that can achieve high power-efficiencies attainable by the SMC when realized using a target CMOS process.

We present in this paper a proposed high-efficiency Class-E power amplifier (PA) for RF Polar transmitters. The PA embodies a proposed novel matching network (MN) with three salient features. First, it is digitally-controlled, and can directly receive the digital Amplitude Modulation (AM) input data to the PA without the need for a conventional supply modulator. Second, the MN performs high-efficiency dynamic load modulation, where load impedance seen by the PA is varied by the MN according to the AM data, and simultaneously, this load impedance is also ensured by the MN to satisfy the zero-voltage-switching condition at the PA to result in high-efficiency operation. Third, it has a novel architectural design that can employ on-, or off-chip inductors, or both inductor types; high quality-factor bond-wires can therefore be used as the inductors to improve the efficiency. The proposed PA with the MN is designed using a 40 nm CMOS technology. Simulation results at 2.4 GHz and 1.1 V supply show that the PA achieves a high power efficiency (drain efficiency) of 48% at peak output power of 17 dBm.

We propose a novel high-rate low-power hybrid window analog-to-digital converter (HWADC) for monolithic digitally-controlled switched-mode dc-dc converters. Conventional Window ADCs are generally based on either voltage-controlled delay lines or ring oscillators. These ADCs usually have a small window size (input voltage range) and a low sampling rate (<;10 MHz) in order to reduce the required IC area and the power dissipation. The proposed HWADC employs a novel hybrid architecture that is a hybrid of delay-lines and ring-oscillators. The HWADC can achieve a large window size with a very high conversion rate, a small IC area, and low power dissipation. Further, the HWADC operates entirely based on digital logic, and is simple to realize using digital cells. The proposed HWADC is designed using a 65 nm CMOS process. Its IC area is 0.005 mm2. Simulation results at 1.2 V supply show that the HWADC can achieve a window size up to 1.2 V (configurable from 0.7 V to 1.9 V) at 250 MHz conversion rate and ~770 μW power dissipation. At the maximum window size of 1.2 V, the quantization step is 50 mV, or equivalently, a resolution of ~4.5 bits.

We propose a novel Variable-Delay Window ADC (VDWADC) design for digitally-controlled switched-mode dc-dc converters. In conventional Window ADCs based on the voltage-controlled delay line, the input voltage supplies the delay line. Thus, the conversion speed slows down when the input voltage decreases. The VDWADC is based on delay lines whose supply voltages are independent of the supply voltage. Hence, when the input voltage decreases, the conversion speed does not slow down. The VDWADC is simulated using 180 nm CMOS process and a supply voltage of 1.8 V. It achieves a quantization step of 0.05 V, or equivalently, a resolution of ~5.2 bits.

We propose to employ the Randomized Wrapped-Around Pulse Position Modulation scheme (RWAPPM) to mitigate the switching-frequency harmonics at the output signal of filterless digital Class D audio amplifiers. The conventional Pulse Width Modulation schemes (PWMs) typically have a non-zero common-mode voltage that contributes to the radiated Electromagnetic Interference (EMI), and generate high switching-frequency harmonics that dissipate extra power at the speaker and also contribute to the radiated EMI. We simulate and compare the RWAPPM (2-level) against the PWMs and a reported randomized modulation scheme. The 2-level RWAPPM has zero common-mode voltage, and amongst the modulation schemes, it features the highest attenuation of the switching-frequency harmonics, highest out-of-band Spurious Free Dynamic Range (22 dBc), and a relatively high Signal to Noise and Distortion Ratio (57 dB) at the output voltage.

We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce the clock speed from 10 GHz to 625 MHz. The lower clock speed allows the use of standard cells for designing the digital computational circuits of the FD DAC. The critical building blocks of the FD DAC are laid-out in a 65 nm CMOS process. The post-layout simulation results show that the Signal to Noise and Distortion Ratio and the in-band Spurious-Free Dynamic Range of the output signal are 36 dB and 44 dBc respectively.

In this paper, we propose an acoustic noise suppression system with reduced musical artifacts for digital hearing instruments (aids). The proposed system features the capabilities to detect, estimate and suppress the acoustic noise corrupting an input speech. The algorithms in the system consist of two noise detections, an enhanced parametric spectral subtraction, a noise attenuation and transition smoothing window, and an automatic gain control. Simulation results on several stationary and nonstationary noise show that our acoustic noise suppression system is capable of improving signal-to-noise ratio by > 9 dB and reducing musical artifacts.