Blue-noise stacked error diffusion (BSED) is a high-quality multi-level halftoning (multitoning) algorithm based on the blue-noise dithering model. This algorithm transforms a multitoning task into multiple error diffusion halftoning tasks, each producing a sub-halftone with inter-layer dependencies. These sub-halftones are stacked together to form the final visually pleasing multitone with blue-noise characteristics. In this research, the significant potential for parallelizing this multitoning algorithm inspires the design of a novel parallel raster image processor (NPRIP) for highly efficient execution, capable of producing an output pixel every six clock cycles at a clock frequency of 200 MHz. A hardware prototype based on the Xilinx Zynq SoC implements our raster image processor design on the FPGA within the SoC. The prototype is also capable of a conventional software implementation of the BSED algorithm running on the ARM CPU within the SoC. Output images from the prototype are successfully validated in both the spatial and frequency domains. Benchmark results demonstrate a consistent speedup exceeding$30\times $with FPGA co-processing compared to conventional sequential execution on the ARM CPU, reaching a maximum processing speed of 3.963 megapixels per second.

Emerging network-level services, such as ephemeral state processing (ESP), provide end systems with the ability to control the way in which their packets are processed at routers in the network. Supporting user-defined per-packet processing at today's wire-speeds requires significant computational power. Special-purpose application specific integrated circuit (ASIC) chips offer the performance, but not the extensibility needed to support these, evolving services. In our previous work, we explored the use of programmable (general-purpose) network processors as a potential solution. Although network processors are easily extensible, they pay a performance penalty for that flexibility. In this paper, we explore a third approach; the use of programmable logic devices (PLD) that combine the flexibility of a network processor with the performance of an ASIC. We describe a PLD implementation of the ESP service, discuss the challenges involved, and present performance numbers showing significant speedups over our previous network processor implementation.

A parallel algorithm, called PARALLEX, which uses a conflict resolving method, has been developed for the switchbox routing problem in a parallel processing environment. PARALLEX can achieve a very high degree of parallelism by generating as many processes as nets. Each process is assigned to route a net, which bears the same identification number as the process. If conflicts are found for the current route of a net, then that process classifies the set(s) of conflict segments into groups that are identified by the various types of conflict(s) within each group. Each process with conflicts finds partial solutions by resolving every conflict of a group in the path-finding procedure and merges them with the solutions from other processes, which may or may not have conflicts, to make a conflict-free switchbox. The speed-up for 7and 19-net problems were 4.7 and 10, respectively.>

A parallel algorithm, called PARALLEX, which uses a conflict resolving method, has been developed for the switchbox routing problem in the parallel processing environment. PARALLEX can achieve a very high degree of parallelism by generating as many processes as nets. Each process is assigned to route a net, which bears the same identification number as the process. If any conflict is found for the current route of a net, then each process classifies the conflict segments with groups by their relations. Each process finds partial solutions, and merges them with the partial solutions from other processes to make a conflict-free switchbox. The speed-ups for 7-nets and 19-nets problem were 4.7 and 10 respectively.>

A control algorithm is developed and implemented for a three-stage Clos network which results in using a multiple-chip approach. The system will be nonblocking in the strict sense and completely self-routing, i.e. the controller for the network will reside in the network and not in a separate computer that runs a program that controls switches to the interconnect array. Intermodule communication required for network operation is described followed by a discussion of how the number of network inputs/outputs may be varied. A delay model of the network is developed.>