This work proposes a broadband transition from tapered microstrip line-to-substrate-integrated waveguide (SIW) using parallel half-mode SIW (HMSIW) for C/X-band applications. The proposed transition comprises four sections: a microstrip feed, tapered microstrip line, tapered parallel HMSIWs, and a waveguide section (SIW). Placing the parallel HMSIWs section between the tapered microstrip line section and the SIW part improves the S-parameters characteristics of the near-cut-off frequency. The HMSIWs section has a lower cut-off frequency than the SIW part, about 4.6 GHz. The lower cut-off- frequency is obtained by gradually altering the electromagnetic field mode to reduce reflection. Which helps convert from TEM mode to TM conversion. The proposed transition is designed, simulated, fabricated, and experimentally verified in order to compare between simulated and experimental results. For the back-to-back laboratory prototype of the transition, the experimental return loss results are less than 20 dB in the 4.6 to 11 GHz frequency range. At the same time, the measured minimum insertion loss is lower than 0.37 dB (maximum: 1.51 dB).

The concept of the corrugated via-wall substrate-integrated waveguide (CV-WSIW) reported by the same authors earlier has now been extended to the mm-wave frequency range, and the transitions for this category of SIWs from microstrip line (ML) are presented in this work. A new design of enhanced CV-WSIW for 18-40 GHz frequency range is proposed. The design includes a tapered section of the microstrip line and two rows of metallic vias with the gap between them. They are providing a better impedance match and reduced overall loss. The proposed design offers improved performance in terms of broadband, return loss (RL), insertion loss (IL), and total loss (TL). The laboratory prototypes are developed, and the obtained simulation results show a close agreement with the measured results. The experimental results show the minimum RL of 22dB, IL of 0.22-0.42dB, a fractional bandwidth of 75.80%, a figure-of-merit of 967.9, and the TL below 20% for ML/CV-WSIW transition within 18-40GHz range. Three additional ML/CV-WSIW transitions were also designed and tested, so that four tested transitions cover 8-60GHz range; an additional fifth transition was simulated only in 60-140GHz range.

This paper proposes a non-iterative method for the design of Radio Frequency Energy Harvesters (RFEHs) with maximum power conversion efficiency (PCE) at any given input power level. Because of the non-linear interdependency of the rectifier’s input impedance and its input voltage to matching network’s and rectifier’s parameters, the design of an RFEH with maximum efficiency requires numerous lengthy transient simulations of the entire energy harvester. Splitting the design space into two separate spaces which only interact with each other through the input voltage of the rectifier, the design goal can now be redefined to finding an optimum input voltage amplitude that maximizes the efficiency of the rectifier while enabling maximum power transfer from antenna to the input of the rectifier at the same time. Using the proposed method, the number of the required simulations to find optimum design values is significantly reduced compared to all previous methods reported in the literature, which also has been experimentally verified by designing three battery-loaded RFEHs at different input power levels in TSMC’s 130nm CMOS process. To further accelerate the design process, closed-form equations to calculate the efficiency and the input resistance of the rectifier are derived for the battery-loaded Dickson charge pump rectifiers.

This paper proposes the Corrugated Via-Wall Substrate Integrated Waveguide (CVWSIW) (with enhanced performance compared to the traditional SIW) and the transitions to this newly proposed CVWSIW from a conductor-backed coplanar waveguide (CB-CPW). The CB-CPW slot lines and the gap between two metallic via rows play a prominent role in widening the bandwidth and reducing the loss. The CB-CPW-CVWSIW transition is initially designed in the 4–8 GHz (C-band) range. Following the same design procedure, the transitions are made for other five different bands to cover the frequencies from 2 to 40 GHz. Improved performance in terms of bandwidth, insertion loss, and total loss is the benefit of the designed transitions with the proposed CVWSIW. Laboratory prototypes of the transitions are fabricated and experimentally measured to cross verify the simulation results. The measured results show, for example, the minimum return loss of 15 dB, maximum insertion loss of 0.36 dB, and fractional bandwidth of 62.16% for C-band.

This paper presents a Tapered Tunable Transmission Line (Tapered TTL) phase shifter that achieves a higher area efficiency than conventional Tunable Transmission Line (TTL) phase shifters while maintaining the same phase shift range with similar insertion losses. A systematic methodology is provided for the optimum design of the proposed phase shifter to maximize its area efficiency while providing the desired phase shift range and satisfying the maximum allowed input/output return and insertion losses. To verify the efficacy of the proposed solution, an eleven-cell phase shifter is fabricated in a standard 65-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the measurement results are reported. The fabricated circuit provides a 180-degree phase shift over the frequency range of 16.5 to 31 GHz with an average insertion loss of 7.2 dB. The proposed design presents a 25 percent reduction in the chip area per unit delay in comparison to the conventional design with the same average insertion loss.

The paper considers a new class of filters with transfer functions providing equal step-response overshoots for all filter orders. This class of filters is derived using Bessel polynomials. The proposed procedure indicates also that Bessel filters are part of a wide class of polynomial filters with prescribed step-response overshoot. The example considered in the paper describes the set of filters, from second to eight order, all having the step-response overshoot equal to 5%. The paper presents the transfer functions of the filters, their frequency responses in the passband and stopband, special features of these responses in the transition zone, and gives the calculated step-response transients.

The paper describes evaluation of drain current harmonics in a MOS transistor operating in moderate inversion and strong saturation. The dependence of the drain current on the gate-source and drain-source voltages is described using a simplified “reconciliation” model developed by Y. Tsividis. Then, in the proposed model the current components corresponding to the terms depending exponentially on normalized gate-source and/or drain-source modulating sinusoidal voltage are evaluated using modified Bessel functions. This approach allows one to omit the small-signal requirement for modulating signals, and calculate the first, second and third harmonics of the drain current caused by the gate-source or drain-source voltages and also find the intermodulation terms. The results are applied to the design of low-distortion low-voltage amplifiers. The recommendations are confirmed by simulations.

A new transistor model is used for design of two LDO regulators using a differential stage loaded by a current amplifier and the voltage feedback. The first LDO has a constant bias current, the second LDO has an additional adaptable bias circuit controlled by the load current. The LDOs are analyzed and compared. When the load is absent, the transistors in both circuits are operating in weak inversion; when the load is increasing the pass transistors in both circuits are moving to strong inversion. It is shown that in these LDOs the output voltage may be higher than the input reference voltage at very small load currents, and the circuits start “to follow” the input voltage only being loaded with a load current depending on the bias and LDO loop gain. The circuits were designed for 130 nm CMOS technology and their operation was verified using CADENCE simulation tool.

It is shown that if a rational function F (s) does not change when 1/ s is substituted instead of s then F (s) is the rational function of s + (1/ s). If the transfer function is a ratio of recursive (symmetric) polynomials, the application of this property can simplify the network synthesis, and, in case of filter synthesis, may result in new filter configurations. In addition, the method chosen for the proof can be used to create new filter transfer functions with useful characteristics. Examples are provided.

The paper describes calculation of the first, second and third harmonics of the output voltage in a MOS transistor stage operating in moderate inversion (common source stage is taken as an example). The dependence of drain current on the gate-source voltage is approximated on the basis of “reconciliation” model proposed by Y. Tsividis and using the term corresponding to saturation operation. Then, the definition of moderate inversion is introduced considering a special series expansion for the function ln2(x). To simplify the calculations we consider the first two terms only for this expansion. Then the harmonic coefficients are obtained by routine calculations. The results of calculations were verified by simulations. The results are in a reasonable agreement; in particular, the presence of the zero value for the third harmonic is confirmed both in calculations and simulations.

The paper describes an extension, at the approximation level, of shunt-peaking technique to increase the filter/amplifier bandwidth. The frequency dependent delay function of a Bessel filter and the modifications of this function consisting in deleting one or more frequency terms in the delay function numerator are considered as “squared-moduli” for a group of filters with transmission zeroes. Using a standard procedure of restoration one finds the transfer functions of this group. The number of filters in each group is defined by the order of the denominator. The paper provides the transfer functions parameters, frequency properties and the parameters of step-transient responses for the filter orders from two to six.

The paper describes and analyzes a new class of filter/amplifier transfer functions. The denominator polynomials of these all-pole transfer functions are calculated via the sum of two Lommel polynomials Rn,μ(z) and Rn-1,ν(z) of orders n and n-1 with different indices μ and ν correspondingly. The proposed wide class of transfer functions may be considered as a generalization of Bessel transfer functions. Indeed for the particular choice of μ= 1/ 2 and ν= 3/ 2 the proposed filters are coinciding with Bessel amplifiers/filters. Using different values of μand ν allow one to modify the transfer function, obtain a desirable step-response overshoot and find the required overshoot- or rise-time-bandwidth exchange. This flexibility is especially useful for design of wideband amplifiers.

The application of time-varying root-locus (TVRL) algorithm for transient analysis of electronic circuits with potentially unstable operating points is presented. The TVRL algorithm calculates the dynamic movement of evolving characteristic equation roots by computing them at a sequence of time instants during the circuit transient. This TVRL indicates the existence of potentially unstable operating points. An LC-filter with Q-enhancement is used as example to demonstrate the dynamics of the circuit characteristic equation roots during power supply transient.

The paper considers the linear feedback systems built around cut-inserted ideal transformers. It is shown that introducing the second additional transformer in cascade connection with the first one and doing the cut in the wire between the transformers one may reduce this method to the previously known Cut-Insertion Theorem (CIT) method. The cut-inserted ideal transformer method is reduced to the second form of the cut-inserted two-port including a voltage source on one side of the cut and a current source on the other side. Then, in the usual way, one obtains the parameters of the feedback system of order two (i.e. having two essential nodes). This system requires consideration of three loops; it may be further analyzed using Mason's rules.

The paper considers a new class of polynomial filters with transfer functions calculated via a recurrent relationship. The procedure starts choosing two kernel algebraic ratios u0(s) = 1 and u1(s) = 1 + 1 / s where s is the complex variable. Further ratios are obtained via the recurrent relationship un+1(s) = [(2n + d) / s]un(s) + un-1(s) where n ≥ 1 and d is a parameter. The numerators of these ratios are taken as denominator polynomials for filter transfer functions. When d = 1 these polynomials are coinciding with the Bessel polynomials. The corresponding filters (or Bessel filters) have a very small step-response overshoot (less than 1%). When d ≠ 1 (the paper considers the range of 0 ≤ d ≤ 1), and is decreasing, the step-response overshoot is increasing. For d = 0 it becomes about 10% as in Butterworth filters. The proposed filters are transitional between Bessel and Butterworth and called here as BeBut filters.

The paper clarifies the difficulties occurring in definition of loop gain in linear networks. The cut-insertion theorem allows one to obtain the parameters of the feedback system resulting from insertion into a cut the two-port providing preservation of the currents and voltages in the rest of the network. Using this theorem for different cuts one can describe the same network by different feedback systems. The characteristic equation of these systems is invariant, yet their loop gains are profoundly different. An example further analyses these difficulties. Some recommendations for the choice of the cut place and correct loading of the cut are given.

A quadrature oscillator based on two RC oscillators with capacitive coupling is proposed and analyzed. The capacitive coupling has the advantages of being noiseless and not increasing the power dissipation. Simulation results show that the oscillation frequency increases proportionally to the coupling capacitances, which is the opposite of what happens in capacitive coupled LC oscillators. Measurements on a 130 nm CMOS circuit prototype validate the theory of the coupling mechanism. The phase-noise is −115 dBc/Hz @ 10 MHz offset, and the FoM is −155.3 dBc/Hz, which is comparable to the best state-of-the art RC oscillators, yet the dissipated power is about four times less.

The paper demonstrates how the pulse h(t), the Laplace transform H(s) of which is an algebraic ratio with poles and zeros located in the left half of the s-plane, can be transformed into a pulse described by the first semi-period of the function sinmt (0 ≤ t ≤ π) where t is normalized time. A realizable transfer function of the network which makes this transformation possible is calculated. The examples given describe the calculation procedure and demonstrate some pitfalls of the approach.

The on-chip oscillator operation can be verified in a contactless way if the oscillator tank inductance is also used as a transmitting antenna. When the probing (receiver) antenna located on the test head is close to the oscillator, both antennas together may be considered as a transformer. The receiving antenna moving to and from the oscillator disturbs the oscillation frequency and amplitude, and these disturbances are registered by the measuring device connected to the receiving antenna. These disturbances, which are not occurring in ordinary oscillators with constant components, are evaluated using the equivalent circuit of thus formed transformer. The variation of frequency and the primary and secondary amplitudes as functions of distance between antennas are calculated. The results are experimentally verified with the oscillator realized in 0.13 μm CMOS technology.

A compact 2.0-11.0GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) using tunable active inductors for suppressing in-band (over 4.8-6.0 GHz) WLAN interference signals is presented. In the proposed LNA, the active inductor in series with a small capacitor forms an active LC resonator which rejects or notches the undesired signals at the resonance frequency. Employing multiple resonators in the LNA increases the rejection depth. Moreover, the tunability of the active inductors allows for notching the signals over a wide frequency range. Designed and simulated in a 90 nm digital CMOS process, the proposed LNA with such active inductors used in notch filters occupies a core chip-area of only 0.0182 mm2. The LNA exhibits an average power gain of 16.5 dB over 2.0-11.0 GHz bandwidth while the rejection of unwanted WLAN interference signals is -44.8 dB at 5.81 GHz. The notch-frequency can be tuned in excess of 4.5-6.6 GHz, and the rejection depth can be increased to -87.5 dB, the highest rejection among the reported notch-filter UWB LNAs.

A new circuit of a magnetic (inductively tuned) RL-multivibrator is proposed. The circuit includes the transconductance amplifier with differential input and single output, and the RL-bridge circuit. The amplifier with limited output current is controlled by the bridge. The output current is distributed between the bridge branches. The resistive branch provides positive feedback and sets the threshold voltage. The inductor branch provides the delay in changing the direction of the amplifier output current. The circuit operation is described, the oscillation wave-forms are calculated, and the oscillation period is found. An example with bipolar transconductance amplifier was realized and tested.

This paper considers two oscillators (van der Pol or Robinson type) synchronized using capacitive coupling. Equations are derived for the oscillation frequency and amplitudes. They show that the frequency of synchronous oscillation is different from the frequencies of individual oscillators. The amplitudes of oscillation are also different: one oscillator becomes a master and the second oscillator becomes a slave. A method of quasilinear approximation is used to evaluate the stability of synchronous oscillation. Simulation results for a 5 GHz oscillator confirm the theoretical analysis.

A fully-active low-noise amplifier (LNA) for ultra-wideband application is presented. Passive on-chip inductor of conventional LNA design is replaced by low-noise active inductor, significantly reducing the total chip area of the proposed CMOS LNA. The core LNA circuit is a cascoded common-source amplifier loaded with an active inductor. Two buffer stages are used to provide the required input and output impedance matching. The amplifier is designed and simulated in 0.13-mum RF CMOS process. It exhibits a forward gain (S21) of 11.2 dB, a noise figure (NF) of 2.2-4.0 dB, and return losses (S11 and S22) of less than -10 dB over the frequency range of 2.0 to 11.2 GHz while consuming only 13.5 mW from a power supply of 1.5 V. The proposed amplifier occupies 0.09 mm of chip area.

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully CMOS compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.

Contrary to what happens with LC oscillators, the increase of coupling in cross-coupled relaxation RC-oscillators leads to a lower quadrature error and lower phase-noise. We present a 2.4 GHz CMOS quadrature relaxation oscillator, and show the measurements confirming this property. Increasing the coupling block gain, the oscillator phase-noise is reduced from -97 dBc/Hz to -104 dBc/Hz @ 1 MHz. The quadrature error is reduced from 4.3deg to 0.8deg. These results show that RC quadrature oscillators may be a practical alternative for RF transceiver applications.

In this paper, a new 3.1 GHz to 11.7 GHz ultra-wide-band (UWB) low-noise amplifier (LNA) is designed in 0.18-μm RF CMOS process. The proposed circuit includes a common-source cascode amplifier followed by an output buffer stage. Special attention is paid to design of inter-stage circuit employing the combined shunt and double-series inductive peaking bandwidth enhancement technique. The amplifier exhibits a forward gain (S21) of 11.0-11.5 dB, a noise figure (NF) of 3.6-4.4 dB, and input return loss (S11) of less than -9.3 dB over the frequency range of 3.1 GHz to 11.7 GHz while consuming only 6.2 mW from a power supply of 1.5 V.

A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.

It is shown that synchronization is similar to amplitude stabilization: both mechanisms involve creation of harmonics and frequency reduction. Synchronization of LC-oscillators can be achieved using similar synchronizing circuits in each oscillator connected in parallel with the tank. The output of the first synchronization circuit is routed to the second oscillator and vice versa. This scheme provides coupling using first, third and other odd harmonics. In addition, introducing coupling between common mode outputs of the synchronizing circuits provides second and other even harmonic coupling. This type of coupling may be also used between common mode outputs of amplitude stabilization circuits. The benefits of using simultaneous first and second harmonic coupling were verified designing a low-power, low phase noise 5 GHz LC oscillator with quadrature outputs. The oscillator phase noise is lower than -121.2 dBc/Hz at 1-MHz offset over the tuning range with a power consumption of 1.8 mW achieving a FOM lower than -192.2 dBc/Hz

A new coupling mechanism is used to synchronize two Van der Pol oscillators. This coupling uses the second harmonic appearing in common mode current of each oscillator. The common mode current is measured by a current mirror, and is amplified by a current amplifier. The amplifier introduces negative feedback, so that the current in the current mirror measuring diode of the first oscillator is nearly equal to the common mode current of the second oscillator, hence the coupling is established. It is shown that the system of two oscillators is described by two differential equations where the coefficients in one equation have the perturbations defined by the second oscillator, and vice versa. The coupling amplifier gain is defined. The developed concepts are demonstrated on a 5 GHz CMOS LC oscillator with quadrature outputs. The oscillator phase noise is lower than -116 dBc/Hz at 1-MHz offset

A method for wireless, noncontact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. The probe consists of a CMOS device with micro antenna structures and transceiver circuits. Each antenna and transceiver circuit is capable of probing one input/output (I/O) site on the DUT. Each I/O site on the DUT is connected to a single antennae and transceiver circuit, which is designed into the DUT. The antennae and transceiver circuits can be incorporated into the DUT without any impact on performance or real estate. The main advantage of noncontact wafer probing is higher reliability (less retest, no pad scrub marks), added functionality (higher test frequencies at higher pin densities), and increased throughput (higher parallelism, reduced alignment tolerance, less maintenance, and less downtime). The wireless probes interface to standard automated test equipment (ATE) while all antenna structures and electronics needed on the DUT are fully CMOS compliant

Mutual compensation of mobility and threshold voltage temperature variations results in a temperature stable bias point of a n-MOS transistor. This effect is used in the proposed voltage reference circuit. The circuit includes an operational amplifier that provides biasing of a diode-connected MOS transistor to the mentioned above point of temperature compensation. Then the voltage at this point is used as the reference voltage setting the operational amplifier output voltage used for the transistor bias.

The paper describes an approach to the design of an isolation electromagnetically coupled DC and AC current sensor and detector. The sensor includes a magnetic multivibrator using one of the coils of a nonlinear transformer. The oscillation duty cycle in this multivibrator changes with the polarity and value of the input signal current in another transformer coil. To detect this duty cycle variation the output voltage of the multivibrator comparator is applied to an integrator and a sample-and-hold amplifier. The circuit was designed to measure the currents in the range from -2.5 to +2.5 mA. The frequency response of the circuit was flat up to 1000 Hz. A digital processor allowing one to represent measurements in a digital form was designed as well.>