Multiprocessor computer systems have proven effective as high performance switching nodes in packet switched data communications networks. They are well suited to performing the required queuing, routing, and scheduling tasks, and can scale upward to provide higher system throughput when combined with software that exploits the parallelism provided by the hardware. This paper describes the packet switch used in the DARPA Wideband Packet Satellite Network and the Butterfly™ Multiprocessor on which it is based.

The Wideband (packet satellite) network is an experimental 3 Mbit/s communications system developed under sponsorship of the Defense Advanced Research Projects Agency and the Defense Communications Agency. This system is being used to evaluate the use of packet transmission for efficient voice communication, voice conferencing, and integration of voice and data over a satellite channel. Each station in the Wideband network consists of an earth terminal (dedicated 5 m antenna plus associated IF/RF equipment), a burst-modem and codec unit, and a station controller. Station controllers provide interfaces to host computers (including packet speech sources) and manage the allocation of the satellite channel on a TDMA demand-assigned basis. TDMA demand-assignment is implemented using a reservation-based packet-oriented protocol capableof handling traffic at multiple priority levels. The channel protocol provides a reservation-per-message mode of service (datagrams) to support transmission from bursty traffic sources and a reservation-per-call mode of service (streams) to support traffic with more regular arrival statisticS (e.g., vioce). A distributed scheduler running in every station controller eliminates the need for a central control station and minimizes network transit delay for datagram transmission as well as stream creation, modification, and deletion. In this paper we describe the protocols and mechanisms upon which the Wideband packet satellite network is based.