This paper presents signal integrity augmentation design techniques in a 64-GBaud transimpedance amplifier (TIA) for coherent optical communication. In the FE-TIA, a bonding wire ringing reduction technique and an input DC current cancellation (IDCC) loop adapted for coherent communication are proposed. In the post amplifiers, a group delay variation (GDV) friendly bandwidth boosting technique is proposed to achieve optimal time domain performance. A non-linearity cancellation technique and a high-linearity gain control approach are proposed in both circuit and system levels. These signal integrity augmentation techniques form a toolkit to solve the design challenges in bandwidth, linearity, GDV, ringing, offset, crosstalk, etc. in high-speed high-order modulation communication. Fabricated in a 90-nm SiGe BiCMOS technology, the TIA shows input-referred noise current density of 15.1 pA/$\surd $Hz, bandwidth of over 40 GHz with GDV less than ±3.75 ps. The TIA gain can be adjusted between$150~\Omega $- 5 K$\Omega $, which enables maximum overload input current of 3 mApp. The total harmonic distortion (THD) is less than 3% and the crosstalk between two channels is less than -3 dB. The chip consumes 264 mW from 3.3 V supply.

This paper presents a 320×240 indirect time of flight (I-ToF) image sensor with 5.6μm×5.6μm 2-Tap pixel in 110nm process. The readout channel offset cancellation and nonlinearity suppression techniques are proposed to achieve high-precision detection. The measured relative precision is 1% at a 5m target distance and non-linearity is below 1.02%. The chip also integrates LVDS and I2C interface for data transmission and Laser control. This work effectively improved the ranging accuracy with a simple method.

In this paper, we present a linear optical receiver for 112-Gb/s PAM-4 optical link. We propose a transimpedance front-end that optimizes thermal noise, power supply noise rejection, linearity and bandwidth altogether. The pseudo-differential structure is employed to achieve both low thermal noise and good power supply noise rejection. A transimpedance amplifier (TIA) gain control technique is proposed to improve linearity at both topology and transistor level while maintaining stability. An NIC-CTLE combo extends bandwidth with optimized frequency response. Designed in a 130nm SiGe BiCMOS process, the receiver realizes 37 GHz total bandwidth and input-referred noise of 19.8 pA/√Hz. The transimpedance gain can vary from 70 dB Ω to 50 dBΩ, which enables maximum input overload current of 1.8 mApp with <; 5% THD at differential output swing of 600 mVpp. The receiver consumes 77mA from 3.3V supply.

The effects of supply-induced frequency variations on single-ended tuning LC voltage-controlled oscillator (VCO) which degrade the jitter performance of the clock are investigated. The first-order impact on the supply sensitivity is that the varactor's effective capacitance varies with the supply voltage, with other second-order impacts attributed to commonly used capacitive bank and cross-coupled pairs. A compensation technique based on complementary varactors to improve the supply sensitivity of single-ended tuning LC VCO is proposed with no extra power dissipation, nor phase noise degradation within the relative frequency band of interest, along with the discussion on the operating principle of the compensation technique. Both the NMOS cross-coupled and complementary cross-coupled LC VCOs have been designed, demonstrating robust supply-insensitive performance over process, voltage, and temperature (PVT) variations. Prototyped oscillators were fabricated in a 0.18-μm CMOS process to verify both the theoretical analysis and the effectiveness of the proposed technique. Measurement results show that the compensated topologies exhibit more than 93% reduction in periodic jitter versus the noncompensated counterparts, with the figures of merit (FoMs) among the best compared with previous supply insensitive works.

A low-power stacked 4×25 Gb/s optical receiver with cooperative power supply regulators is presented in this paper. Different from conventional parallel channels, the proposed stacked 4 channels fully exploit the supply headroom of the optical module and share a common supply current. Thanks to this current reuse scheme, excellent power efficiency is achieved. In addition, cooperative power supply and photodiode (PD) biasing schemed are co-developed. Each receiver channel is constituted by a transimpedance amplifier (TIA) and a main amplifier (MA), realizing 56.8 dBΩ gain and 27.3 GHz bandwidth. Designed in 28 nm CMOS, the stacked 4×25 Gb/s optical receiver as well as integrated the power regulators together consume 15.4 mW from 3.3 V supply, which translates to state-of-the-art power efficiency of 0.154 mW/Gb/s.

A 56Gb/s PAM-4 linear optical receiver with low noise and high linearity is presented. The fully integrated receiver comprises a transimpedance amplifier (TIA), a variable gain amplifier (VGA), an output buffer, auxiliary analog loops and on-chip bias circuitry. As will be shown, low noise and high linearity often contradict each other, thus both the TIA and VGA implement novel gain control techniques for linear operation while realizing low noise design, making them favorable for PAM-4 signal amplification. Designed and implemented in 45nm SOI CMOS technology, the receiver accomplishes state-of-the-art input-referred noise current of 1.8μArms, 74.4dB transimpedance gain and 23GHz bandwidth while consuming 37mW. The dynamic range achieved is 29dB, enabling large input overload of 0.8mA for PAM-4 compliant signaling.

Active rectifier with comparators (CMPs) is often used in wireless power transmission (WPT) systems. However, it suffers from low power conversion efficiency (PCE) in light load condition and multiple pulse problem (MPP) due to the CMPs with delay compensation. In this paper, a novel active rectifier with delay time controller is proposed to solve both issues. A current control delay line (CCDL) is introduced to adjust the rising and the falling edges of the gate voltages of the NMOS (Fgns), controlled by a negative feedback loop consisting of a switched-capacitor (SC) sample module and a supply independent bias current controller (IB controller). The proposed rectifier is designed with a standard 0.18μm CMOS process. Post-layout simulation results show that the delay time controller consumes only 34μΑ, which is much smaller than the power consumptions induced by controller with CMPs, thus significantly enhancing the PCE of the rectifier. The PCE of the rectifier is higher than 88% in the whole load range from 629μΑ to 32.1mA, and exceeds 92% when load resistance Rl varies from 100Ω to 1200Ω. A peak PCE of 95.3% is achieved when Rl is 200Ω and Vac is 2V.