Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mitigating the scaling effects and maintaining the reliability above a certain threshold. Many of these schemes rely on incorporating different types of redundancy at the device, gate, and system level, which inevitably affect the area, power, and delay parameters. To optimize the tradeoff between these conflicting parameters, an accurate and efficient reliability EDA tool is needed. Such a tool would help circuit designers compare different reliability schemes and select the one that achieves the target reliability margins while having minimum impact on the other design parameters. However, the enormous size and the complexity of today's logic circuits make accurate calculation of the circuit's reliability a very challenging and time-consuming process. This paper introduces a novel, accurate, and efficient algorithm for circuit reliability estimation. The algorithm improves accuracy by taking the effect of reconvergent fan-out nodes into consideration, while improving efficiency by implementing a multithreaded approach for node evaluation. Simulation results show that the proposed algorithm is efficient and more accurate than other reliability estimation algorithms currently proposed in the literature.

Scaling the CMOS devices deep into the nanorange reduces their reliability margins significantly. Consequently, accurately calculating the reliability of digital nanocircuits is becoming a necessity for investigating design alternatives to optimize the trade-offs between area-power-delay and reliability. However, accurate reliability calculation of large and highly connected circuits is complex and very time consuming. This paper proposes a progressive consensus-based algorithm for identifying the worst reliability input vectors and the associated critical logic gates. Improving the reliability of the critical gates helps circuit designers to effectively improve the circuit overall reliability while having a minimal impact on the traditional power-area-deal design parameters. The accuracy and efficiency of the algorithm can be tuned to fit a variety of applications. The algorithm scales well with circuit size, and is independent of the interconnect complexity and the logic depth. Extensive computational results show that the accuracy and the efficiency of the proposed algorithm are better than the most recent results reported in the literature.

As the sizes of CMOS devices rapidly scale deep into the nanometer range, the manufacture of nanocircuits will become extremely complex and will inevitably introduce more defects, including more transient faults that appear during operation. For this reason, accurately calculating the reliability of future designs will be extremely critical for nanocircuit designers as they investigate design alternatives to optimize the tradeoffs between area-power-delay and reliability. However, accurate calculation of the reliability of large and highly connected circuits is complex and very time consuming. This paper presents a complete solution for estimating logic circuit reliability bounds with high accuracy in reasonable time, even for very large and complex circuits. The solution combines a novel criticality scoring algorithm to rank the reliability of individual input vectors with a heuristic search to find the input vector having the lowest reliability. The solution scales well with circuit size, and is independent of the interconnect complexity or the logic depth. Extensive computational results show that the speed of our method is orders of magnitude faster than exact solutions provided by Bayesian network exact inferences, while maintaining identical or sufficiently close accuracy.

Over the last decades, nanotechnology had established itself as the upcoming revolution in science and technology. The ability of manipulating material at the atomic and molecular levels allowed nanotechnology to open an entirely new paradigm of devices and products. The worldwide market of products incorporating nanotechnology achieved $245 million in 2009 and estimated to reach $6 trillion by 2020. In the semiconductor industry several new nanodevices have been proposed to replace the classical CMOS devices that have been used over the last four decades. These new nanodevices have shown significant potential to overcome the fundamental limits of CMOS devices, and to advance the semiconductor industry further. However, limited educational resources and processes are available to prepare future nanotechnology engineers and scientists to integrate these promising nanodevices into the main semiconductor manufacturing streams. This paper proposes new learning structures and processes to propagate nanotechiology learning resources over the pervasive Web. The proposed approach is illustrated by a case study centered around the manufacturing of future nanodevices. We adopt standard structures and processes to organize and navigate through digital instructional contents, such as IEEE LOM and IMS LD. In doing so, we aim at streamlining the propagation of reusable repositories across the open Web to facilitate the integration of nanotechnology learning resources into the rising social trend of massively open online courses (or MOOCs)

Teaching programming skills to novice students is very challenging. They usually have to deal with many difficulties including learning the syntax of the programming language along with the logic of devising a solution to an existing problem. They also need to develop many skills to enable them building an abstract mental model of a certain problem, device a solution for it, then implement and test the solution in a correct way. Moreover, they need to understand how programs are compiled and executed. This paper presents our experience of introducing the iPad as a pedagogical tool in our introductory C programming course. The aim was to help students overcome some of their difficulties, and to improve their learning experience. The results of two surveys as well as the official student evaluation of teaching scores show that it was a positive experience in general. The iPad was integrated into the classroom with minimal effort, and provided a friendly environment that facilitated group work, creativity, and independent learning.

Denial of Service (DoS) attacks are important topics for security courses that teach ethical hacking techniques and intrusion detection. This paper presents a case study of the implementation of comprehensive offensive hands-on lab exercises about three common DoS attacks. The exercises teach students how to perform practically the DoS attacks in an isolated network laboratory environment. The paper discuses also some ethical and legal issues related to teaching ethical hacking, and then lists steps that schools and educators should take to improve the chances of having a successful and problem free information security programs.

Assessment of curriculum outcomes represents a critical stage of any degree program evaluation to support continuous academic improvement. The collection, aggregation and analysis of assessment data are notoriously complex and time-consuming processes. Several actors are involved across the assessment workflows, which we propose to streamline in the context of a portal-based approach. We first describe a model for capturing and propagating assessment data across the assessment cycle as well as tracking potential deficiencies in the assessed program. We then describe our portal-based implementation of the proposed model in the context of an ACM-based IT Curriculum program which assessment processes respond to ABET accreditation requirements. We reveal the results of our assessment experience using the proposed model and the corresponding in-house developed portal. We show the corrective curricular actions facilitated by our assessment tool to close the assessment cycle.

Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PFGATE=const.) , or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PFDEV); 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculatePFGATEdue to different types of faults and/or defects, and to estimate the effects of enhancingPFDEVonPFGATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 105, 10, and 1010respectively, while the area is increased by less than 50%.

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.

Our goal in this paper is to study the performance of the game-theoretic power control algorithms for wireless data introduced by Saraydar et al [1] in two realistic channels: (a1) fast flat fading channel and (a2) Slow flat fading channel. The fading coefficients under both (a1) and (a2) are studied under an appropriate small scale channel model that is used in the CDMA cellular systems, namely Nakagami channel model. To do so, we derive a closed- form expression of the average utility function which represents the number of bits received correctly at the receiver per one Joule expended. Then, using this expression we study the existence, uniqueness of Nash equilibrium (NE), and the social desirability of NE in the Pareto sense.

In this paper, we compare two different Boolean function reduction methods in order to justify the analytical model of the Monte Carlo data for Boolean function complexity. We use a binary decision diagram (BDD) complexity model (proposed earlier) and weigh it against the complexity behavior generated by Synopsys Design Compiler (DC). We use this synthesis tool (that utilizes a standard cell library) to generate RTL hardware description of Monte Carlo circuits as gate-level netlists. The two reduction methods (model and DC) transform an arbitrary function into a much-reduced representation of the same function. The comparison confirms that the behavior of Boolean function complexity using the model and the DC is visually and statistically similar; the similarity holds true for BDDs representing functions comprising a wide range of variables and minterms.

This paper presents a thorough analysis of brain's connectivity from the perspective of the latest interpretation of Rent's rule, and using neurological data. While at first sight the brain might seem to outperform most of the known network topologies, a closer look will reveal that in fact it does not. From another perspective, the brain will seem to be just on the border of the latest range of Rent's rule values, while neurological data will show that it is almost right on the average. We conclude that, among quite a few network topologies, the crossbar (for very small sizes) and the cube connected cycles are highly competitive contenders for future brain-inspired nanoarchitectures.

This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The study will provide insights into different parameters that affect the reliability of these FAs. The paper will also present estimates for the power consumption and the speed achieved by some of these FAs. All these simulations show that minimum fan-in majority gates FAs are: (i) more reliable; (ii) faster; while also (Hi) consuming less power (than a standard XOR-based FA). The detailed reliability results will be extrapolated to link to the probability of failure of the elementary (nano-)devices. Such speed-power-reliability performance analyses are certainly essential and very timely for a better characterization of circuit designs, but also for identifying those designs amenable to future nanoelectronic technologies. The main conclusions are that small fan-in majority gates perform better than standard Boolean gates in all cost functions: speed, power, area, and reliability.

Validation of microprocessor designs is one of the most complex and expensive tasks in today’s system-on-chip development process. Conditions to be validated are identified by the architects, the designers, and the validation team. Testing for these conditions is a must for the processor to tape out especially these conditions with high priorities. A significant bottleneck in the validation process of such systems is that not enough time is normally given to the final coverage phase and computing cycles becomes very precious resource. Thus, intelligent selection of test-cases that achieves the best coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents two novel techniques for testcase selection and condition coverage. The proposed techniques make two important contributions. First, it addresses the generalization of covering problems to partial covering. Second, it finds a good set of test-cases that fulfills the target coverage under different scenarios, while taking into considerations operations priority, and computing cycles required by each test-case.

Design validation is one of the most complicated and costly tasks in today's system-on-chip development process. Conditions to be validated are identified by the architects, the designers, and the validation team. Testing for these conditions is a must for the design to tape out especially for high priority conditions. A significant bottleneck in such systems is that not enough time is normally given to the final coverage phase which makes computing cycles very precious. Thus, intelligent selection of test vectors that achieve the target coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents a two-phase genetic algorithm for test vector selection and condition coverage. The proposed algorithm significantly outperforms other proposed heuristic algorithms in different scenarios, while taking into considerations the conditions priorities and computing cycles required by each test vector.

Abstract Wireless networks are evolving to include Internet access to interactive multimedia and video conferencing as well as traditional services such as voice, email and web access. These new applications can demand large amounts of network resources, such as bandwidth, to achieve the highest levels of quality (e.g. picture quality). In conjunction with this trend, charging and resource allocation systems must evolve to explicitly consider the trade‐off between resource consumption and the Quality of Service (QoS) provided. This paper proposes a novel QoS‐based charging and resource allocation framework. The framework allocates resources to customers based on their QoS perceptions and requirements, thereby charging fairly while improving resource allocation efficiency. It also allows the network operators to pursue a wide variety of policy options, including maximizing revenue or using auction or utility‐based pricing. Copyright © 2003 John Wiley & Sons, Ltd.