This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board.

With the development of Deep Learning, Convolutional Neural Network (CNN) is widely used for visual tasks, such as image or object recognition and classification. Many studies have been conducted to deploy a CNN architecture on Field Programmable Gate Array (FPGA) to achieve high speed in academics and industries. However, due to the rapid innovation of the CNN architecture, deploying different CNNs on FPGA faces the challenges of hardware design as well as the FPGA hardware implementation. In our paper, we propose a general-purpose CNN framework targeted for industries to flexibly build their CNNs in the FPGA computing clusters. This framework is based on our proposed mathematical model and provides the rapid prototyping methods of construing various CNN architectures. The CNN architecture constructed by the framework can be deployed on any FPGA available in the cluster according to the requirements of the industrial applications. The usage of the framework requires no hardware expertise for industries, and all evaluations such as timing, resource utilization of the inferred model are provided by a mathematic model.

With the emergence of connected and autonomous vehicles along with their growing integration of available services, in-vehicle electronic architecture is no longer able to work up to its full potential. Each new service demands processing and computation traditionally handled by a new Electronic Control Unit (ECU). Modern vehicle design tends to be architected around ECU gathered either by feature or by physical location to minimize wiring. Both architectures cannot exploit capabilities of Processing Units (PU) in term of resources such as MIPS and memories.In this paper, we propose a novel approach for the management of these resources by introducing multi-agent systems. This concept consists of integrating IoT-A architectures (implementing agents as close as possible to the hardware), and Avatar architectures (virtualizing the representation of the hardware in high level: Cloud and Edge computing). The result of this work is the emergence of a new EdgeAgent architectural proposal to extend vehicle management and functionalities while considering the environment for vehicles of the future.

Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on FPGAs, which improve the evaluation time and precision when compared to other solutions. There are different architectures of FPGA-based NoC evaluation tools. Details are scattered among several papers, making a comparative analysis hard to accomplish. This paper presents a comprehensive overview of FPGA tools for NoC evaluation. Our analysis covers aspects like network architecture, traffic generation and interface to the host PC. This provides insight on the platforms and their usefulness for different NoC evaluation tasks.

Network-on-Chip (NoC) is an interesting communication fabric for multi processing element architectures that benefits from the parallelism of algorithms. We present a method that uses a symbolic execution technique to extract the parallelism of an application to be mapped on FPGAs using the flexibility of a NoC communication infrastructure and the properties of a high level programming language. An application specific hardware is then generated using a High Level Synthesis flow. We provide a dedicated mechanism for data paths reconfiguration that allows different applications to run on the same set of processing elements. Thus, the output design is programmable and has a processor-less distributed control. This approach of using NoCs enables us to automatically design generic architectures that can be used on FPGA servers for High Performance Reconfigurable Computing.We validate our method on binomial tree applications used for option pricing on FPGAs.

The Networks-on-Chip (NoCs) are currently the most appropriate communication structure for many-core embedded systems. An FPGA-based emulation platform can drastically reduce the time needed to evaluate a NoC, even if it is composed by tens or hundreds of distributed components. These components should be timely managed in order to execute an evaluation traffic scenario. There is a lack of standard protocols to drive FPGA-based NoC emulators. Such protocols could ease the integration of emulation components developed by different designers. In this paper, we evaluate a light version of SNMP (Simple Network Management Protocol) to manage an FPGA-based NoC emulation platform. The SNMP protocol and its related components are adapted to a hardware implementation. This facilitates the configuration of the emulation nodes without FPGA-resynthesis, as well as the extraction of emulation results. Some experiments highlight that this protocol is quite simple to implement and very efficient for a light resources overhead.

Networks-on-Chip (NoCs) are currently the most appropriate communication structure for many-core embedded systems. Those networks support many real-time data flows. Their performance depends directly on the routing strategy. In this paper, we present a new congestion-aware routing algorithm (FlexOE) based on a simple and flexible scheme of prioritized sets of rules. These sets of rules are based on the Odd-Even turn model, minimal paths checking, congestion information from adjacent routers and availability of output path. The algorithm FlexOE developed is integrated on a Hermes NoC, and then implemented on an FPGA. The evaluation results point out that FlexOE has greater performances than reference algorithms for some test scenarios and similar performances for others test scenarios.

The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced exploration time. Emulation requires multi-FPGA platform as the resources for large NoC is important and cannot be handling by one FPGA. In the same time, SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC, making emulation more complex. This paper presents a case study of the deployment of the 2D NoC structure to 3D. A design flow is proposed for the automatic generation of a NoC targeting 3D on multi-FPGAs. The flow integrates emulation blocks used for the validation and exploration on the NoC. With this automatic aided tool, the designer can evaluate and explore the NoC architecture and extract performances of the NoC regardless of the multi-component platform. One may expect a communication performance improvement using an adapted partitioning of the NoC, as highlighted by the results given in this paper.

C-based design techniques and methodologies have been proposed to tackle the complexity of heterogeneous embedded systems. The heterogeneity comes in the functionalities and the implementation requirements. Various IPs with diverse complexities and functionalities can be selected to build an heterogeneous system. However, implementation hints should be available at the highest possible level of abstraction. In this paper, we conduct a quantitative evaluation of C-based design of heterogeneous embedded systems and point out the impact of behavioral synthesis on partitioning.

Particle image velocimetry (PIV) algorithms aim at flow visualisation and dynamic flow measurement. All existing PIV techniques are computing intensive and are mainly used in critical conditions. For a given experimental environment, several parameters must be set so that PIV algorithm must be parameterised. A dedicated architecture is therefore unsuitable unless it is adaptive. The aim of this work is to prove that our generic and adaptive FPGA-based system for real-time PIV applications previously designed can easily be modified when some parameters vary. From a unique structure and library of resources, the designer adapts the architecture according to the parameters. Time and resource prediction models help the designer to find the most suitable structure before the implementation process and ensure only one implementation without feedback. As a result, the design flow is fast and reliable

In this paper, an efficient architecture for particle image velocimetry algorithm is proposed. The aim of this work is the design of a system of chip FPGA that can be adapted to application characteristics (size of image, pixel clock frequency...). From these specifications, the designer defines the suitable number of processing modules. Required resources and execution time can also be predicted before the implementation process that makes the design flow faster and more secure

The aim of our work is to achieve a rapid prototyping dedicated to mixed architectures, made up of one multi-DSP part (software) and a FPGA architecture (dedicated hardware). We have determined a complete codesign methodology enabling to implement a complete digital signal or image processing line. The starting description associated with this methodology, is only a functional description, represented by a data flow graph. This global process developed for an automatic implementation enables the user to develop complex applications at a high level onto a complex architecture without any implementation pre-requirements.